migrate jelib->delib
[fleet.git] / chips / omegaCounter / 40nm / electric / redFive.delib / inv.sch
1 HredFive|8.10k
2
3 # Cell inv;1{sch}
4 Cinv;1{sch}||schematic|1021415734000|1248729106644||ATTR_Delay(D5G1;HNPX-12;Y-5;)I100|ATTR_X(D5FLeave alone;G1;HNOLPX-12;Y-4;)S1|ATTR_drive0(D5G1;HNPTX-12;Y-6;)Sstrong0|ATTR_drive1(D5G1;HNPTX-12;Y-7;)Sstrong1|ATTR_verilog_template(D5G1;NTX24.5;Y-11;)Snot ($(drive0), $(drive1)) #($(Delay)) $(node_name) ($(out), $(in));|prototype_center()I[0,0]
5 INMOS;1{ic}|NMOS@1||0|-5|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
6 IPMOS;1{ic}|PMOS@1||0|6|||D0G4;|ATTR_Delay(D5G1;NOJPX3.5;Y-2;)S@Delay|ATTR_X(D5FLeave alone;G1.5;NOLPX3.5;Y0.5;)S@X
7 Ngeneric:Facet-Center|art@0||0|0||||AV
8 NOff-Page|conn@0||19|0||||
9 NOff-Page|conn@1||-17.5|0||||
10 NGround|gnd@0||0|-12||||
11 Iinv;1{ic}|inv@0||25|13|||D0G4;|ATTR_Delay(D5G1;NPX2;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.5;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
12 IinvI;2{ic}|inv@1||25|7|||D5G4;|ATTR_Delay(D5G1;NPX1.75;Y-2;)I100|ATTR_X(D5FLeave alone;G1.5;NOLPX1.25;Y2;)S1|ATTR_drive0(P)Sstrong0|ATTR_drive1(P)Sstrong1
13 NWire_Pin|pin@0||-4|0||||
14 NWire_Pin|pin@1||0|0||||
15 Ngeneric:Invisible-Pin|pin@2||0|16.5|||||ART_message(D5G2;)S[P to N width ratio is 2 to 1]
16 Ngeneric:Invisible-Pin|pin@3||28.5|-6|||||ART_message(D5G2;)S[X is drive strength,P and N drive strengths are equal]
17 Ngeneric:Invisible-Pin|pin@4||0|18.5|||||ART_message(D5G2;)S[one-parameter fixed size (non-LE) inverter]
18 Ngeneric:Invisible-Pin|pin@5||0.5|22|||||ART_message(D5G6;)S[inv]
19 NWire_Pin|pin@6||-4|6||||
20 NWire_Pin|pin@7||-4|-5||||
21 NPower|pwr@0||0|11.5||||
22 Awire|net@0|||0|conn@0|a|17|0|pin@1||0|0
23 Awire|net@1|||0|pin@0||-4|0|conn@1|y|-15.5|0
24 Awire|net@2|||900|pin@6||-4|6|pin@0||-4|0
25 Awire|net@3|||900|pin@0||-4|0|pin@7||-4|-5
26 Awire|net@4|||2700|gnd@0||0|-10|NMOS@1|s|0|-7
27 Awire|net@5|||2700|NMOS@1|d|0|-3|pin@1||0|0
28 Awire|net@6|||0|NMOS@1|g|-3|-5|pin@7||-4|-5
29 Awire|net@7|||2700|PMOS@1|s|0|8|pwr@0||0|11.5
30 Awire|net@8|||0|PMOS@1|g|-3|6|pin@6||-4|6
31 Awire|net@9|||2700|pin@1||0|0|PMOS@1|d|0|4
32 Ein||D5G2;|conn@1|a|I
33 Eout||D5G2;|conn@0|y|O
34 X