chips/omegaCounter/40nm/electric/redFive.delib/inv2iCTLn.sch

   1 HredFive|8.10k
   2
   3 # Cell inv2iCTLn;1{sch}
   4 Cinv2iCTLn;1{sch}||schematic|993433994000|1248729331835||ATTR_X(D5G2;HNPX-19;Y-5;)I1|prototype_center()I[0,0]
   5 INMOS;1{ic}|NMOS@1||0|0.5|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
   6 INMOS;1{ic}|NMOS@2||0|9|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I175|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X*2.0
   7 IPMOS;1{ic}|PMOS@1||0|22|||D0G4;|ATTR_Delay(D5G1;NPX3.5;Y-2;)I100|ATTR_X(D5G1.5;NOJPX3.5;Y0.5;)S@X
   8 Ngeneric:Facet-Center|art@0||0|0||||AV
   9 NOff-Page|conn@0||-11|22||||
  10 NOff-Page|conn@1||-12|9||||
  11 NOff-Page|conn@2||-12|0.5||||
  12 NOff-Page|conn@3||12.5|16||||
  13 NGround|gnd@0||0|-6.5||||
  14 Iinv2iCTLn;1{ic}|inv2iCTL@0||15|27.75|||D0G4;|ATTR_X(D5G1.5;NPX1.5;Y2;)I2
  15 NWire_Pin|pin@0||0|20.5||||
  16 NWire_Pin|pin@1||-2.5|22||||
  17 Ngeneric:Invisible-Pin|pin@2||0|33|||||ART_message(D5G3;)S[inv2iCTLn]
  18 NWire_Pin|pin@3||0|16||||
  19 NPower|pwr@0||0|28||||
  20 Awire|net@0|||0|PMOS@1|g|-3|22|conn@0|y|-9|22
  21 Awire|net@1|||0|NMOS@1|g|-3|0.5|conn@2|y|-10|0.5
  22 Awire|net@2|||900|NMOS@1|s|0|-1.5|gnd@0||0|-4.5
  23 Awire|net@3|||1800|PMOS@1|g|-3|22|pin@1||-2.5|22
  24 Awire|net@4|||900|pwr@0||0|28|PMOS@1|s|0|24
  25 Awire|net@5|||2700|PMOS@1|d|0|20|pin@0||0|20.5
  26 Awire|net@6|||1800|pin@3||0|16|conn@3|a|10.5|16|SIM_verilog_wire_type(D5G1;)Strireg
  27 Awire|net@7|||2700|NMOS@1|d|0|2.5|NMOS@2|s|0|7
  28 Awire|net@8|||900|pin@3||0|16|NMOS@2|d|0|11
  29 Awire|net@9|||900|PMOS@1|d|0|20|pin@3||0|16
  30 Awire|net@10|||0|NMOS@2|g|-3|9|conn@1|y|-10|9
  31 Ectl||D5G2;X-4;|conn@1|y|I
  32 EinN||D5G2;|conn@2|a|I
  33 EinP||D4G2;|conn@0|a|I
  34 Eout||D5G2;|conn@3|y|O
  35 X