1 ********************** TSMC 90nm Header **************************
3 ******************************************************************
4 * Set Process, Voltage and Temperature corner
5 ******************************************************************
10 *.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT
11 *.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_RES
12 *.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_18
13 *.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_na18
14 *.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_esd
15 *.lib '/import/async/cad/process/tsmc090/spice_models/models/cln90g_lk.l' TT_DIO_18
18 .lib '/import/async/cad/process/tsmcsun045/sun_spice_models/1.01/models/toplevel_cln40gp.l' TOP_TT
23 .param sup=0.9 * Supply voltage
24 .temp 80 * Temperature
26 ******************************************************************
27 * Standard Parameters and Options
28 ******************************************************************
33 .param strong0=0 * Used in verilog, just needs to be defined to run hspice
34 .param strong1=1 * Used in verilog, just needs to be defined to run hspice
36 .options ACCT OPTS post
41 .param AVT0N = AGAUSS(0.0, '0.01 / 0.1' , 1)
42 .param AVT0P = AGAUSS(0.0, '0.01 / 0.1' , 1)
43 .param ABN = AGAUSS(0.0, '0.02 / 0.1' , 1)
44 .param ABP = AGAUSS(0.0, '0.02 / 0.1' , 1)
46 ******************************************************************
48 ******************************************************************
49 .hsimparam HSIMDCINIT=0
50 .hsimparam HSIMVDD=0.9
53 * .param HSIMOUTPUT=fsdb
54 * .param HSIMOUTPUTTBL=rawfile
58 * .param HSIMPRINTSIMSTATUS=1
59 * .param HSIMOUTPUTFLUSH=1n
63 * for extracted-layout simulation
66 * I used to use HSIMSPEED=5, but the omega counter has simulation artifacts at that level
69 * defaults -- play with these?
71 * .param HSIMPORTV=0.001
72 * .param HSIMPORTCR=0.01
81 * these are here to keep hsim from "optimizing away" the signals we care about
97 * .print v(xmarinagu@0.xoutdockw@3.xmarinaou@1.xoutputDo@0.xoutM1Pre@0.xoutDockP@0.xoutDockC@0.*)
98 * .print v(marinagu@0/jtagcent@0/*)