3 This document describes the correlation between publicly documented
4 logic, I/O, and routing resources within the Atmel AT40k/94k family
5 of chips and bits in the bitstreams needed to program them.
7 Our goal is to make this information available to the public without
8 restriction on its use, for the purpose of creating automated tools
9 which generate bitstreams.
12 Statement of Public Knowledge
14 The Knowledge encapsulated in this document was derived by formal
15 scientific experimentation, using only information generally
16 available to the public. Extreme care which has been taken to
17 ensure that the process did not violate any copyright, trademark,
18 trade secret, or patent statutes. No licensing contracts or
19 non-disclosure agreements were entered into by the parties involved
20 in this endeavor, nor did they have access to any confidential
23 This document is part of the Public Domain; its authors surrender
24 claim to copyright on it.
29 If you find errors in this document, please correct them and add the
30 date and a short description of the correction to the table below.
31 This will assist in merging changes made in disjoint derivitaves.
33 2005.08.12 [gosset] Initial revision
34 2006.03.12 [megacz] Swapped {L1,L0}->W, FB->{L0,L1}, {H0->L0,H1->L1}
35 2006.03.13 [megacz] Fixed lowest bit of z=00000000; it should be "1"
36 2006.03.13 [megacz] Corrected meaning of z-octet bits 2-4 in IOBs
37 2006.03.13 [megacz] Added constant zeroes in IOB section
38 2006.04.15 [megacz] un-swapped FB->{L0,L1}
42 The Atmel AT40k Datasheet describes in great detail the resources
43 available in the AT40k as well as the FPGA portion of the AT94k
44 (which is functionally identical and uses the same binary
45 configuration format).
47 The configuration space used to control these resources consists of
48 a collection of independent octets arranged in a sparse 24-bit
49 address space. This document correlates those bits with the
50 resources described in the Datasheet.
52 The process of configuring the device consists of writing these
53 octets into the configuration memory. Once the desired
54 configuration octets are known, the procedures for loading them into
55 configuration memory are well documented in Atmel Documents 1009 and
58 Each data octet "D" has a 24-bit address, divided into three address
59 octets "X", "Y", and "Z". In general, the X and Y address octets
60 are related to the physical position of the resource, while the Z
61 octet is related to the type of resource being addressed.
65 We will use the notation A->B to indicate that setting the
66 corresponding configuration bit high causes source A to drive wire
67 B, and the notation A<>B to indicate that a pass gate between A and
68 B is enabled. The notation ~A or ~A->B indicates a configuration
69 bit controlling A or causing A to drive B is *active low*
72 We will use the following terms to describe routing resources.
73 They vary slightly from Atmel's documentation, but are less
76 X, Y, W, Z The cell's inputs
77 XO, YO The X and Y outputs from the cell (to its neighbors)
78 N, S, E, W Orthogonal lines: connections to neighboring cells
79 NE,SE,NW,SW Diagonal lines: connections to neighboring cells
80 S0..S4 Quad lines: four-cell long routing lines
81 H0..H4 Horizontal quad lines
82 V0..V4 Vertical quad lines
83 L0..L4 Switchbox ports: the wires joining FB,H0..H4,V0..V4,X,Y,Z,W
84 G0a..G4b Global lines: eight-cell long routing lines, in two sets (a+b)
85 FB The cell's internal feedback line
86 R The cell's internal register
87 C The cell's "center" output; can drive the X or Y outputs
88 ZM The "Z-mux"; the mux which drives the cell's register input
89 WM The "W-mux"; the mux which drives the third input to the LUTs
90 XL, YL The output of the X,Y-LUTs
91 IA The "internal and" gate (W & Z)
96 Although the exact interpretation of the X and Y octets depends on
97 the resource type (Z octet), in most cases the X and Y octets are
98 the cartesian coordinates of the logic cell nearest to the desired
99 resource (0,0 is the lower-left hand logic cell). This section
100 describes the significance of the Z and D octets for such resources.
103 - The most significant four bits of the Z octet are 0000 for these bits
104 - If WZ->WM and FB->WM are both low, then W->WM.
105 - If ZM->R and YL->R are both low, then the XL->R
106 - The ZM->C and ZM->FB bits are used to bypass the register (when high).
107 - ~SET bit controls the set/reset behavior of the register; 0=set, 1=reset
109 +----+--------+--------+--------+--------+--------+--------+--------+--------+
111 +----+--------+--------+--------+--------+--------+--------+--------+--------+
112 |0000| V4->L4 | H4->L4 | FB->L2 | FB->L3 | FB->L1 | FB->L0 | FB->L4 | 1 |
113 +----+--------+--------+--------+--------+--------+--------+--------+--------+
114 |0001| ZM->R | YL->R | WZ->WM | FB->WM | ZM->C | ZM->FB | C->XO | C->YO |
115 +----+--------+--------+--------+--------+--------+--------+--------+--------+
116 |0010| L4->Z | L4->Y | L3->Z | L2->Z | L1->Z | L0->Z | V4->OE | H4->OE |
117 +----+--------+--------+--------+--------+--------+--------+--------+--------+
118 |0011| L2->W | L3->W | L4->W | L4->X | L0->W | L1->W |H2a<>V2a|H3b<>V3b|
119 +----+--------+--------+--------+--------+--------+--------+--------+--------+
120 |0100| N->Y | S->Y | W->Y | E->Y | L0->Y | L1->Y | L2->Y | L3->Y |
121 +----+--------+--------+--------+--------+--------+--------+--------+--------+
122 |0101| SW->X | NE->X | SE->X | NW->X | L0->X | L1->X | L2->X | L3->X |
123 +----+--------+--------+--------+--------+--------+--------+--------+--------+
124 |0110| X-LUT truth table, inverted |
125 +----+--------+--------+--------+--------+--------+--------+--------+--------+
126 |0111| Y-LUT truth table, inverted |
127 +----+--------+--------+--------+--------+--------+--------+--------+--------+
128 |1000| V3->L3 | H3->L3 | H2->L2 | V2->L2 | V1->L1 | H0->L0 | V0->L0 | H1->L1 |
129 +----+--------+--------+--------+--------+--------+--------+--------+--------+
130 |1001|H1a<>V1a|H0a<>V0a|H0b<>V0b|H4a<>V4a|H4b<>V4b|H1b<>V1b|H3a<>V3a|H2b<>V2b|
131 +----+--------+--------+--------+--------+--------+--------+--------+--------+
133 +----+--------+--------+--------+--------+--------+--------+--------+--------+
134 |0001| 1 | 1 | 1 | 1 | ~SET | 1 | 1 | 1 |
135 +----+--------+--------+--------+--------+--------+--------+--------+--------+
140 Clocking, reset, and inter-sector repeaters are resources which are
141 not specific to a particular cell. As such, their X,Y addressing is
142 slightly different. These resources are addressed by the cartesian
143 coordinates of the cell above or to the right of the resource, with
144 an additional twist: for resources in vertical channels, the
145 X-coordinate is shifted right by two bits (divided by four); for
146 resources in horizontal channels, the Y-coordinate is shifted right
147 by two bits (divided by four).
149 The most significant three bits of the Z-octet for a sector resource
150 are set to 001; the next bit (fourth most significant) is set to 0
151 for horizontal channels and 1 for vertical channels.
153 One sector wire and one global wire enter each side of each
154 repeater, for a total of four connections. Each connection has an
155 associated four-bit code which indicates if that connection is
156 driven by the repeater, and if so, which connection to the repeater
159 000 - driver disabled
160 100 - source is global wire on the other side of the repeater
161 010 - source is sector wire on the other side of the repeater
162 001 - source is other connection on the same side of the repeater
164 Example: a code of 001 for the left-hand side sector wire driver
165 means that the source of the driver should be the left hand side
166 global wire. A code of 010 for the top sector wire driver means that
167 the source of the driver should be the bottom sector wire.
172 CC+ = sector clock of the sector below this one
173 InvSC = invert the clock source (CC or S4) before driving SC
175 +----------+--------+--------+-----+-----+------+-----+-----+------+
176 | Z octet | D octet |
177 +----------+--------+--------+-----+-----+------+-----+-----+------+
178 | 001_0000 | 1 | 0 | Left/Top G4 | Left/Top S4 |
179 +----------+--------+--------+-----+-----+------+-----+-----+------+
180 | 001_0001 | 0 | S4->CR | Right/Bottom G4 | Right/Bottom S4 |
181 +----------+--------+--------+-----+-----+------+-----+-----+------+
182 | 001_0010 | 1 | 0 | Left/Top G3 | Left/Top S3 |
183 +----------+--------+--------+-----+-----+------+-----+-----+------+
184 | 001_0011 | 1 | 1 | Right/Bottom G3 | Right/Bottom S3 |
185 +----------+--------+--------+-----+-----+------+-----+-----+------+
186 | 001_0100 | 1 | 0 | Left/Top G2 | Left/Top S2 |
187 +----------+--------+--------+-----+-----+------+-----+-----+------+
188 | 001_0101 | SC->CC+| S3->SC | Right/Bottom G2 | Right/Bottom S2 |
189 +----------+--------+--------+-----+-----+------+-----+-----+------+
190 | 001_0110 | 1 | 0 | Left/Top G1 | Left/Top S1 |
191 +----------+--------+--------+-----+-----+------+-----+-----+------+
192 | 001_0111 | 1 | 1 | Right/Bottom G1 | Right/Bottom S1 |
193 +----------+--------+--------+-----+-----+------+-----+-----+------+
194 | 001_1000 | 1 | 0 | Left/Top G0 | Left/Top S0 |
195 +----------+--------+--------+-----+-----+------+-----+-----+------+
196 | 001_1001 | InvSC |~SC->CC+| Right/Bottom G0 | Right/Bottom S0 |
197 +----------+--------+--------+----+--------+----+-----+--------+---+
202 Although block memories are shown in the lower right hand corner of
203 each sector in the Atmel Datasheets, they are conceptually addressed
204 by the cartesian coordinate of the cell in the lower *left* hand
205 corner of the sector. Furthermore, both coordinates are shifted
206 right two bits (divided by four).
208 The significance of the "D" octet for a given block memory depends
209 on its position; if it falls in an odd sector-column (4-7, 12-15,
210 etc), use the first chart; otherwise, use the second chart.
212 USECLK = the memory is synchronous
213 ENABLE = the memory is enabled
214 DUAL = enable both ports on a dual-ported memory
218 +--------+------+------+------+------+--------+--------+--------+---------+
220 +--------+------+------+------+------+--------+---------+--------+--------+
221 |01000000| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
222 +--------+------+------+------+------+--------+---------+--------+--------+
223 |01000001| 1 | 1 | 1 | 1 | USECLK | ~ENABLE | ENABLE | ENABLE |
224 +--------+------+------+------+------+--------+---------+--------+--------+
228 +--------+------+------+------+------+--------+--------+--------+--------+
230 +--------+------+------+------+------+--------+--------+--------+--------+
231 |01000000| 1 | 1 | 1 | 1 | USECLK | DUAL | ~DUAL | ENABLE |
232 +--------+------+------+------+------+--------+--------+--------+--------+
233 |01000001| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
234 +--------+------+------+------+------+--------+--------+--------+--------+
239 The Z octet for I/O resources always its most significant three bits
240 set to 011. The next bit is 1 for North/South IO Blocks and 0 for
241 East/West IO Blocks. The next bit is always 0, and the bit
242 following that is set to 0 for primary (orthogonally connected)
243 IOBs, 1 for secondary (diagonally connected) IOBs.
245 S = Sector wires of this cell
246 S+ = Sector wires of next cell
247 S- = Sector wires of previous cell
248 G = Global wires of this cell
249 G+ = Global wires of next cell
250 Output = Allow output from this IOB
251 OE = when low, output is always enabled
252 OEM = 7 bits, one-hot encoded, chooses input to output-enable mux
253 USEOEM = when low, ignore the output enable mux
254 Delay = amount of delay to add; can be 0, 1, 3, or 5
255 Slew = slew time: 11=fast, 10=med, 01=slow
256 Pull = 00=pullup, 11=pulldown, 01=none
258 +--------+--------+--------+------+-------+-------+--------+--------+--------+
260 +--------+--------+--------+------+-------+-------+--------+--------+--------+
261 |011_0_00| Schmit | Slew |~G2->CR| 0 | Pull | 0 |
262 +--------+--------+--------+------+-------+-------+--------+--------+--------+
263 |011_0_01|REG->OUT| 0 | OE | Output Mux |
264 +--------+--------+--------+------+-------+-------+--------+--------+--------+
265 |011_0010| Added Delay (primary) |PRI->S-| PRI->G+| PRI->G | PRI->S |
266 +--------+--------+--------+------+-------+-------+--------+--------+--------+
267 |011_0110| Added Delay (secondary) |SND->S | SND->S+|PRI->REG|SND->REG|
268 +--------+--------+--------+------+-------+-------+--------+--------+--------+
269 |011_0_11| OEM | USEOEM | OEM |
270 +--------+--------+--------+------+-------+-------+--------+--------+--------+
273 Global Clock/Reset Networks
275 To drive a column clock from one of the eight global clock/reset
276 networks, set the corresponding bit in the desired column:
278 +--------+--------+--------+
279 |Z octet |X octet |Y octet |
280 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
281 |10100000| column |00000000| CK1 | CK2 | CK3 | CK4 | CK5 | CK6 | CK7 | CK8 |
282 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
286 The following configuration resources are not fully understood, but
287 the values below appear to work.
289 +--------+--------+--------+
290 |Z octet |X octet |Y octet |
291 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
292 | |00000000|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
293 |10100001|00010111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
294 | |00101111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
295 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
296 |11010000|00000000|00000000| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
297 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
298 |11010011|00000000|00000000| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
299 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+