3 This document describes the correlation between publicly documented
4 logic, I/O, and routing resources within the Atmel AT40k/94k family
5 of chips and bits in the bitstreams needed to program them.
7 Our goal is to make this information available to the public without
8 restriction on its use, for the purpose of creating automated tools
9 which generate bitstreams.
12 Statement of Public Knowledge
14 The Knowledge encapsulated in this document was derived by formal
15 scientific experimentation, using only information generally
16 available to the public. Extreme care which has been taken to
17 ensure that the process did not violate any copyright, trademark,
18 trade secret, or patent statutes. No licensing contracts or
19 non-disclosure agreements were entered into by the parties involved
20 in this endeavor, nor did they have access to any confidential
23 This document is part of the Public Domain; its authors surrender
24 claim to copyright on it.
29 If you find errors in this document, please correct them and add the
30 date and a short description of the correction to the table below.
31 This will assist in merging changes made in disjoint derivitaves.
33 2005.08.12 [gosset] Initial revision
34 2006.03.12 [megacz] Swapped {L1,L0}->W, FB->{L0,L1}, {H0->L0,H1->L1}
35 2006.03.13 [megacz] Fixed lowest bit of z=00000000; it should be "1"
36 2006.03.13 [megacz] Corrected meaning of z-octet bits 2-4 in IOBs
37 2006.03.13 [megacz] Added constant zeroes in IOB section
38 2006.04.15 [megacz] un-swapped FB->{L0,L1}
39 2007.09.01 [megacz] fix column clocking bits
43 The Atmel AT40k Datasheet describes in great detail the resources
44 available in the AT40k as well as the FPGA portion of the AT94k
45 (which is functionally identical and uses the same binary
46 configuration format).
48 The configuration space used to control these resources consists of
49 a collection of independent octets arranged in a sparse 24-bit
50 address space. This document correlates those bits with the
51 resources described in the Datasheet.
53 The process of configuring the device consists of writing these
54 octets into the configuration memory. Once the desired
55 configuration octets are known, the procedures for loading them into
56 configuration memory are well documented in Atmel Documents 1009 and
59 Each data octet "D" has a 24-bit address, divided into three address
60 octets "X", "Y", and "Z". In general, the X and Y address octets
61 are related to the physical position of the resource, while the Z
62 octet is related to the type of resource being addressed.
66 We will use the notation A->B to indicate that setting the
67 corresponding configuration bit high causes source A to drive wire
68 B, and the notation A<>B to indicate that a pass gate between A and
69 B is enabled. The notation ~A or ~A->B indicates a configuration
70 bit controlling A or causing A to drive B is *active low*
73 We will use the following terms to describe routing resources.
74 They vary slightly from Atmel's documentation, but are less
77 X, Y, W, Z The cell's inputs
78 XO, YO The X and Y outputs from the cell (to its neighbors)
79 N, S, E, W Orthogonal lines: connections to neighboring cells
80 NE,SE,NW,SW Diagonal lines: connections to neighboring cells
81 S0..S4 Quad lines: four-cell long routing lines
82 H0..H4 Horizontal quad lines
83 V0..V4 Vertical quad lines
84 L0..L4 Switchbox ports: the wires joining FB,H0..H4,V0..V4,X,Y,Z,W
85 G0a..G4b Global lines: eight-cell long routing lines, in two sets (a+b)
86 FB The cell's internal feedback line
87 R The cell's internal register
88 C The cell's "center" output; can drive the X or Y outputs
89 ZM The "Z-mux"; the mux which drives the cell's register input
90 WM The "W-mux"; the mux which drives the third input to the LUTs
91 XL, YL The output of the X,Y-LUTs
92 IA The "internal and" gate (W & Z)
97 Although the exact interpretation of the X and Y octets depends on
98 the resource type (Z octet), in most cases the X and Y octets are
99 the cartesian coordinates of the logic cell nearest to the desired
100 resource (0,0 is the lower-left hand logic cell). This section
101 describes the significance of the Z and D octets for such resources.
104 - The most significant four bits of the Z octet are 0000 for these bits
105 - If WZ->WM and FB->WM are both low, then W->WM.
106 - If ZM->R and YL->R are both low, then the XL->R
107 - The ZM->C and ZM->FB bits are used to bypass the register (when high).
108 - ~SET bit controls the set/reset behavior of the register; 0=set, 1=reset
110 +----+--------+--------+--------+--------+--------+--------+--------+--------+
112 +----+--------+--------+--------+--------+--------+--------+--------+--------+
113 |0000| V4->L4 | H4->L4 | FB->L2 | FB->L3 | FB->L1 | FB->L0 | FB->L4 | 1 |
114 +----+--------+--------+--------+--------+--------+--------+--------+--------+
115 |0001| ZM->R | YL->R | WZ->WM | FB->WM | ZM->C | ZM->FB | C->XO | C->YO |
116 +----+--------+--------+--------+--------+--------+--------+--------+--------+
117 |0010| L4->Z | L4->Y | L3->Z | L2->Z | L1->Z | L0->Z | V4->OE | H4->OE |
118 +----+--------+--------+--------+--------+--------+--------+--------+--------+
119 |0011| L2->W | L3->W | L4->W | L4->X | L0->W | L1->W |H2a<>V2a|H3b<>V3b|
120 +----+--------+--------+--------+--------+--------+--------+--------+--------+
121 |0100| N->Y | S->Y | W->Y | E->Y | L0->Y | L1->Y | L2->Y | L3->Y |
122 +----+--------+--------+--------+--------+--------+--------+--------+--------+
123 |0101| SW->X | NE->X | SE->X | NW->X | L0->X | L1->X | L2->X | L3->X |
124 +----+--------+--------+--------+--------+--------+--------+--------+--------+
125 |0110| X-LUT truth table, inverted |
126 +----+--------+--------+--------+--------+--------+--------+--------+--------+
127 |0111| Y-LUT truth table, inverted |
128 +----+--------+--------+--------+--------+--------+--------+--------+--------+
129 |1000| V3->L3 | H3->L3 | H2->L2 | V2->L2 | V1->L1 | H0->L0 | V0->L0 | H1->L1 |
130 +----+--------+--------+--------+--------+--------+--------+--------+--------+
131 |1001|H1a<>V1a|H0a<>V0a|H0b<>V0b|H4a<>V4a|H4b<>V4b|H1b<>V1b|H3a<>V3a|H2b<>V2b|
132 +----+--------+--------+--------+--------+--------+--------+--------+--------+
134 +----+--------+--------+--------+--------+--------+--------+--------+--------+
135 |0001| 1 | 1 | 1 | 1 | ~SET | 1 | 1 | 1 |
136 +----+--------+--------+--------+--------+--------+--------+--------+--------+
141 Clocking, reset, and inter-sector repeaters are resources which are
142 not specific to a particular cell. As such, their X,Y addressing is
143 slightly different. These resources are addressed by the cartesian
144 coordinates of the cell above or to the right of the resource, with
145 an additional twist: for resources in vertical channels, the
146 X-coordinate is shifted right by two bits (divided by four); for
147 resources in horizontal channels, the Y-coordinate is shifted right
148 by two bits (divided by four).
150 The most significant three bits of the Z-octet for a sector resource
151 are set to 001; the next bit (fourth most significant) is set to 0
152 for horizontal channels and 1 for vertical channels.
154 One sector wire and one global wire enter each side of each
155 repeater, for a total of four connections. Each connection has an
156 associated four-bit code which indicates if that connection is
157 driven by the repeater, and if so, which connection to the repeater
160 000 - driver disabled
161 100 - source is global wire on the other side of the repeater
162 010 - source is sector wire on the other side of the repeater
163 001 - source is other connection on the same side of the repeater
165 Example: a code of 001 for the left-hand side sector wire driver
166 means that the source of the driver should be the left hand side
167 global wire. A code of 010 for the top sector wire driver means that
168 the source of the driver should be the bottom sector wire.
173 SC+ = sector clock of the sector below this one
174 InvSC = invert the clock source (CC or S4) before driving SC
176 Note that you must set both CC->SC in the desired sector and CC->SC+
177 in the sector above the desired sector in order to receive a column
180 +----------+--------+--------+-----+-----+------+-----+-----+------+
181 | Z octet | D octet |
182 +----------+--------+--------+-----+-----+------+-----+-----+------+
183 | 001_0000 | 1 | 0 | Left/Top G4 | Left/Top S4 |
184 +----------+--------+--------+-----+-----+------+-----+-----+------+
185 | 001_0001 | 0 | S4->CR | Right/Bottom G4 | Right/Bottom S4 |
186 +----------+--------+--------+-----+-----+------+-----+-----+------+
187 | 001_0010 | 1 | 0 | Left/Top G3 | Left/Top S3 |
188 +----------+--------+--------+-----+-----+------+-----+-----+------+
189 | 001_0011 | 1 | 1 | Right/Bottom G3 | Right/Bottom S3 |
190 +----------+--------+--------+-----+-----+------+-----+-----+------+
191 | 001_0100 | 1 | 0 | Left/Top G2 | Left/Top S2 |
192 +----------+--------+--------+-----+-----+------+-----+-----+------+
193 | 001_0101 | CC->SC+| S3->SC | Right/Bottom G2 | Right/Bottom S2 |
194 +----------+--------+--------+-----+-----+------+-----+-----+------+
195 | 001_0110 | 1 | 0 | Left/Top G1 | Left/Top S1 |
196 +----------+--------+--------+-----+-----+------+-----+-----+------+
197 | 001_0111 | 1 | 1 | Right/Bottom G1 | Right/Bottom S1 |
198 +----------+--------+--------+-----+-----+------+-----+-----+------+
199 | 001_1000 | 1 | 0 | Left/Top G0 | Left/Top S0 |
200 +----------+--------+--------+-----+-----+------+-----+-----+------+
201 | 001_1001 | InvSC | CC->SC | Right/Bottom G0 | Right/Bottom S0 |
202 +----------+--------+--------+----+--------+----+-----+--------+---+
207 Although block memories are shown in the lower right hand corner of
208 each sector in the Atmel Datasheets, they are conceptually addressed
209 by the cartesian coordinate of the cell in the lower *left* hand
210 corner of the sector. Furthermore, both coordinates are shifted
211 right two bits (divided by four).
213 The significance of the "D" octet for a given block memory depends
214 on its position; if it falls in an odd sector-column (4-7, 12-15,
215 etc), use the first chart; otherwise, use the second chart.
217 USECLK = the memory is synchronous
218 ENABLE = the memory is enabled
219 DUAL = enable both ports on a dual-ported memory
223 +--------+------+------+------+------+--------+--------+--------+---------+
225 +--------+------+------+------+------+--------+---------+--------+--------+
226 |01000000| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
227 +--------+------+------+------+------+--------+---------+--------+--------+
228 |01000001| 1 | 1 | 1 | 1 | USECLK | ~ENABLE | ENABLE | ENABLE |
229 +--------+------+------+------+------+--------+---------+--------+--------+
233 +--------+------+------+------+------+--------+--------+--------+--------+
235 +--------+------+------+------+------+--------+--------+--------+--------+
236 |01000000| 1 | 1 | 1 | 1 | USECLK | DUAL | ~DUAL | ENABLE |
237 +--------+------+------+------+------+--------+--------+--------+--------+
238 |01000001| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
239 +--------+------+------+------+------+--------+--------+--------+--------+
244 The Z octet for I/O resources always its most significant three bits
245 set to 011. The next bit is 1 for North/South IO Blocks and 0 for
246 East/West IO Blocks. The next bit is always 0, and the bit
247 following that is set to 0 for primary (orthogonally connected)
248 IOBs, 1 for secondary (diagonally connected) IOBs.
250 S = Sector wires of this cell
251 S+ = Sector wires of next cell
252 S- = Sector wires of previous cell
253 G = Global wires of this cell
254 G+ = Global wires of next cell
255 Output = Allow output from this IOB
256 OE = when low, output is always enabled
257 OEM = 7 bits, one-hot encoded, chooses input to output-enable mux
258 USEOEM = when low, ignore the output enable mux
259 Delay = amount of delay to add; can be 0, 1, 3, or 5
260 Slew = slew time: 11=fast, 10=med, 01=slow
261 Pull = 00=pullup, 11=pulldown, 01=none
263 +--------+--------+--------+------+-------+-------+--------+--------+--------+
265 +--------+--------+--------+------+-------+-------+--------+--------+--------+
266 |011_0_00| Schmit | Slew |~G2->CR| 0 | Pull | 0 |
267 +--------+--------+--------+------+-------+-------+--------+--------+--------+
268 |011_0_01|REG->OUT| 0 | OE | Output Mux |
269 +--------+--------+--------+------+-------+-------+--------+--------+--------+
270 |011_0010| Added Delay (primary) |PRI->S-| PRI->G+| PRI->G | PRI->S |
271 +--------+--------+--------+------+-------+-------+--------+--------+--------+
272 |011_0110| Added Delay (secondary) |SND->S | SND->S+|PRI->REG|SND->REG|
273 +--------+--------+--------+------+-------+-------+--------+--------+--------+
274 |011_0_11| OEM | USEOEM | OEM |
275 +--------+--------+--------+------+-------+-------+--------+--------+--------+
278 Global Clock/Reset Networks
280 To drive a column clock from one of the eight global clock/reset
281 networks, set the corresponding bit in the desired column:
283 +--------+--------+--------+
284 |Z octet |X octet |Y octet |
285 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
286 |01010000| column |00000000| CK8 | CK7 | CK6 | CK5 | CK4 | CK3 | CK2 | CK1 |
287 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
291 The following configuration resources are not fully understood, but
292 the values below appear to work.
294 +--------+--------+--------+
295 |Z octet |X octet |Y octet |
296 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
297 | |00000000|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
298 |10100001|00010111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
299 | |00101111|00000000| 1 | 1 | 1 | 1 | 1 | 1 | GCK SRC |
300 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
301 |11010000|00000000|00000000| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
302 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+
303 |11010011|00000000|00000000| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
304 +--------+--------+--------+-----+-----+-----+-----+-----+-----+-----+-----+