6 * all user i/os default to pull-up
9 - during reset, FPSLIC drives low
10 - released when ready for config bits
11 - user drives low in order to start config
12 - FPSLIC then drives low when preamble OK
15 - power on or RESET goes low
16 - INIT,CON,LDC,HDC all low
19 - RESET is sampled; when high,
20 - INIT released, pin checked to make sure other devices ok
21 - INIT drifts high due to pullup
23 - CON released (drifts high)
34 - config-to-chip tx/rx
35 - INIT: pulls down if config fails (internal 20kohm pullup)
36 => reusable as user I/O
37 - CON: driven low during reset, released when ready for cfg
38 - user drives this low
41 - M0, M2, CS0, UARTs, CON, RESET, PORTXXX
43 - ExternalXTAL1 needs a pull-down resistor
44 XTAL1<->4.7kohms<->GND
45 - on-chip oscillator; see p41
47 - USB.CLK12 -> FPGA.CCLK ==> manual clock?
48 - USB.CLK12 -> FPGA.XTAL1 ==> manual clock?
61 - OTS (tri-state all user IO)?
65 - HDC (high during configuration)
66 - LDC (low during configuration)
70 - Slave serial: M0=1, M2=0, external source drives CCLK
71 - data applied on rising edge of clock