1 --$ XILINX$RCSfile: xcf32p.bsd,v $
2 -- XILINX Revision: 1.3
3 -------------------------------------------------------------------------------
4 -- Copyright (c) 2006 Xilinx, Inc.
5 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
6 -------------------------------------------------------------------------------
9 -- /___/ \ / Vendor: Xilinx
10 -- \ \ \/ Version: v1.0 (PROM BSDL template version)
11 -- \ \ Application: Generate_Prom_Bsdl_Files.pl, 1.00
12 -- / / Filename: xcf32p.bsd
13 -- /___/ /\ Generated: Wed Oct 11 19:34:15 2006
14 -- \ \ / \ State: State: PRELIMINARY
18 -- Package: GENERIC (using VO48 package as basis)
19 -- Purpose: IEEE 1149.1 BSDL file
23 ------------------------------------------------------------------------------
26 -- Find the latest version of this BSDL file, find technical support answers,
27 -- or find contact information at: http://www.support.xilinx.com
29 ------------------------------------------------------------------------------
30 -- Special Instructions:
32 -- This BSDL file reflects the pre-configuration behavior. To reflect
33 -- the post-configuration JTAG behavior (if any), edit this file as
35 -- 1. Rename file and entity if necessary to avoid name collisions.
36 -- 2. Modify USERCODE value in USERCODE_REGISTER declaration.
37 ------------------------------------------------------------------------------
38 -- BSDL Silicon Validation Information
40 ------------------------------------------------------------------------------
43 generic (PHYSICAL_PIN_MAP : string := "VO48");
61 GND: linkage bit_vector (1 to 7);
69 VCCINT: linkage bit_vector (1 to 3);
71 VCCO: linkage bit_vector (1 to 4);
72 DNC: linkage bit_vector (1 to 11)
75 use STD_1149_1_2001.all;
77 attribute COMPONENT_CONFORMANCE of XCF32P : entity is
80 attribute PIN_MAP of XCF32P : entity is
83 constant VO48: PIN_MAP_STRING:=
106 "GND : (2,7,17,23,31,36,46)," &
107 "VCCINT : (4,15,34)," &
109 "VCCO : (8,30,38,45)," &
110 "DNC : (1,3,14,16,18,35,37,39,40,41,42)";
112 attribute TAP_SCAN_IN of TDI : signal is true;
113 attribute TAP_SCAN_MODE of TMS : signal is true;
114 attribute TAP_SCAN_OUT of TDO : signal is true;
115 attribute TAP_SCAN_CLOCK of TCK : signal is (15.00e+06, BOTH);
117 attribute INSTRUCTION_LENGTH of XCF32P : entity is
120 attribute INSTRUCTION_OPCODE of XCF32P : entity is
121 "BYPASS (1111111111111111)," &
122 "SAMPLE (0000000000000001)," &
123 "PRELOAD (0000000000000001)," &
124 "EXTEST (0000000000000000)," &
125 "IDCODE (0000000011111110)," &
126 "USERCODE (0000000011111101)," &
127 "HIGHZ (0000000011111100)," &
128 "CLAMP (0000000011111010)," &
129 "ISC_ENABLE (0000000011101000)," &
130 "XSC_ENABLEC (0000000011101001)," &
131 "ISC_PROGRAM (0000000011101010)," &
132 "ISC_ADDRESS_SHIFT (0000000011101011)," &
133 "ISC_READ (0000000011111000)," &
134 "ISC_ERASE (0000000011101100)," &
135 "ISC_DATA_SHIFT (0000000011101101)," &
136 "XSC_READ (0000000011101111)," &
137 "XSC_BLANK_CHECK (0000000000001101)," &
138 "ISC_DISABLE (0000000011110000)," &
139 "ISC_NOOP (0000000011100000)," &
140 "XSC_CONFIG (0000000011101110)," &
141 "XSC_CLR_STATUS (0000000011110100)," &
142 "XSC_OP_STATUS (0000000011100011)," &
143 "XSC_MFG_READ (0000000011110001)," &
144 "XSC_CONFIG_PLUS (0000000011110110)," &
145 "XSC_UNLOCK (1010101001010101)," &
146 "XSC_DATA_BTC (0000000011110010)," &
147 "XSC_DATA_WRPT (0000000011110111)," &
148 "XSC_DATA_RDPT (0000000000000100)," &
149 "XSC_DATA_UC (0000000000000110)," &
150 "XSC_DATA_CC (0000000000000111)," &
151 "XSC_DATA_DONE (0000000000001001)," &
152 "XSC_DATA_CCB (0000000000001100)," &
153 "XSC_DATA_BLANK (0000000011110101)," &
154 "XSC_DATA_SUCR (0000000000001110)," &
155 "XSC_ADDRESS_DUMP (0000000011100110)";
157 attribute INSTRUCTION_CAPTURE of XCF32P: entity is
159 -- IR[15:9] = 0000000 (Not used)
160 -- IR[8:7] = Previous ISC Operation Result (10=success; 01=fail; 00/11=N/A)
161 -- IR[6:5] = Erase/Program Result (10=success; 01=fail; 00/11=N/A)
162 -- IR[4] = Erase/Program Status (1=ready; 0=busy)
163 -- IR[3] = ISC/Normal Mode (1=ISC mode; 0=normal download mode)
164 -- IR[2] = 1532 DONE Status For Selected Revision (1 = DONE; 0 = Not DONE)
165 -- IR[1:0] = 01 as defined by IEEE STD 1149.1
167 attribute IDCODE_REGISTER of XCF32P: entity is
169 "0101000001011001" & -- part number
170 "00001001001" & -- manufacturer's id
171 "1"; -- required by IEEE STD 1149.1
173 attribute USERCODE_REGISTER of XCF32P: entity is
174 "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
177 attribute REGISTER_ACCESS of XCF32P : entity is
178 "BOUNDARY (EXTEST, SAMPLE, PRELOAD),"&
179 "BYPASS (BYPASS, HIGHZ, CLAMP, ISC_DISABLE, XSC_CONFIG, XSC_CONFIG_PLUS)," &
180 "DEVICE_ID (IDCODE, USERCODE),"&
181 "ISPENABLE[8] (ISC_ENABLE, XSC_ENABLEC),"&
182 "DATA0[256] (ISC_DATA_SHIFT)," &
183 "ISC_RDATA[256] (ISC_READ),"&
184 "DATA1[8388608] (XSC_READ),"&
185 "ADDRESS[24] (ISC_ADDRESS_SHIFT),"&
186 "ISC_SECTOR[24] (ISC_ERASE, XSC_UNLOCK),"&
187 "DATA_UC[32] (XSC_DATA_UC)," &
188 "ISC_DEFAULT[8] (ISC_PROGRAM, ISC_NOOP, XSC_OP_STATUS, XSC_CLR_STATUS),"&
189 "XSC_MFG[8] (XSC_MFG_READ),"&
190 "BLANK[8] (XSC_BLANK_CHECK, XSC_DATA_BLANK),"&
191 "DATA_BTC[32] (XSC_DATA_BTC),"&
192 "DATA_WRPT[16] (XSC_DATA_WRPT),"&
193 "DATA_RDPT[16] (XSC_DATA_RDPT),"&
194 "DATA_CC[256] (XSC_DATA_CC),"&
195 "DONE[8] (XSC_DATA_DONE),"&
196 "DATA_CCB[16] (XSC_DATA_CCB),"&
197 "DATA_SUCR[16] (XSC_DATA_SUCR),"&
198 "ADDR_DUMP[16] (XSC_ADDRESS_DUMP)";
200 attribute BOUNDARY_LENGTH of XCF32P : entity is
203 attribute BOUNDARY_REGISTER of XCF32P : entity is
204 -- cellnum (type, port, function, safe[, ccell, disval, disrslt])
205 " 0 (BC_1, CE , input, X )," &
206 " 1 (BC_1, CLK, input, X )," &
207 " 2 (BC_1, *, controlr, 0 )," &
208 " 3 (BC_1, OE_RESET, output3, X, 2, 0, Z )," &
209 " 4 (BC_1, OE_RESET, input, X )," &
210 " 5 (BC_1, *, controlr, 0 )," &
211 " 6 (BC_1, CEO, output3, X, 5, 0, Z )," &
212 " 7 (BC_1, *, controlr, 0 )," &
213 " 8 (BC_1, CLKOUT, output3, X, 7, 0, Z )," &
214 " 9 (BC_1, *, controlr, 0 )," &
215 "10 (BC_1, CF , output3, X, 9, 0, Z )," &
216 "11 (BC_1, CF , input, X )," &
217 "12 (BC_1, BUSY, input, X )," &
218 "13 (BC_1, *, controlr, 0 )," &
219 "14 (BC_1, D7, output3, X, 13, 0, Z )," &
220 "15 (BC_1, *, controlr, 0 )," &
221 "16 (BC_1, D6, output3, X, 15, 0, Z )," &
222 "17 (BC_1, *, controlr, 0 )," &
223 "18 (BC_1, D5, output3, X, 17, 0, Z )," &
224 "19 (BC_1, *, controlr, 0 )," &
225 "20 (BC_1, D4, output3, X, 19, 0, Z )," &
226 "21 (BC_1, *, controlr, 0 )," &
227 "22 (BC_1, D3, output3, X, 21, 0, Z )," &
228 "23 (BC_1, *, controlr, 0 )," &
229 "24 (BC_1, D2, output3, X, 23, 0, Z )," &
230 "25 (BC_1, *, controlr, 0 )," &
231 "26 (BC_1, D1, output3, X, 25, 0, Z )," &
232 "27 (BC_1, *, controlr, 0 )," &
233 "28 (BC_1, D0, output3, X, 27, 0, Z )," &
234 "29 (BC_1, REV_SEL1, input, X )," &
235 "30 (BC_1, REV_SEL0, input, X )," &
236 "31 (BC_1, EN_EXT_SEL, input, X )";
238 attribute DESIGN_WARNING of XCF32P : entity is
239 "The XCF32P TAP PAUSE states are not " &
240 "fully compliant with the IEEE 1149.1 specification. The active instruction " &
241 "or data shift register re-captures new values when the TAP is transitioned " &
242 "from a PAUSE state, through the corresponding EXIT2 state, and back to the " &
243 "original SHIFT state. The following are potential methods that can be used " &
244 "to avoid this issue: " &
245 "1. Avoid using the TAP PAUSE-IR or PAUSE-DR state to temporarily pause " &
246 "a shift operation. " &
247 "2. Stop (gate) the TCK within the SHIFT-IR or SHIFT-DR state to pause " &
248 "a the shift operation instead of parking the TAP in the corresponding " &
250 "3. Put this XCF32P device on a separate " &
251 "boundary-scan chain that does not encounter the TAP PAUSE states. " &
252 "Do not drive CF low when CF is connected to the PROGRAM/PROG_B pin of " &
253 "a Virtex, Virtex-E, Virtex-4, Spartan-II, Spartan-IIE FPGA and when " &
254 "the FPGA is in the same boundary-scan chain as this XCF32P. " &
255 "A Low applied to the PROGRAM/PROG_B pin of these FPGAs resets the TAP " &