3 == Ports ===========================================================
10 == TeX ==============================================================
12 == Fleeterpreter ====================================================
13 public void service() { }
14 == FleetSim ==============================================================
16 == FPGA ==============================================================
20 reg ddr2_write_data_push;
21 reg ddr2_read_data_pop;
22 reg [`DATAWIDTH:0] out_d;
24 assign ddr2_addr_r_ = ddr2_addr_r;
25 assign ddr2_isread_ = ddr2_isread;
26 assign ddr2_addr_ = !ddr2_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
27 assign ddr2_write_data_push_ = ddr2_write_data_push;
28 assign ddr2_read_data_pop_ = ddr2_read_data_pop;
29 assign ddr2_write_data_ = { inDataWrite_d[31:5], inDataWrite_d[4], inDataWrite_d[35:0] };
30 // assign ddr2_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0];
31 assign out_d_ = out_d;
33 always @(posedge clk) begin
39 ddr2_read_data_pop <= 0;
44 if (!inAddrRead_r_ && inAddrRead_a) inAddrRead_a <= 0;
45 if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0;
46 if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0;
47 if ( out_r && out_a) out_r <= 0;
49 if (ddr2_addr_r && !ddr2_addr_a) begin
51 end else if (ddr2_addr_r && ddr2_addr_a && !ddr2_isread) begin
55 out_d <= { 1'b1, 37'b0 };
57 end else if (ddr2_addr_r && ddr2_addr_a && ddr2_isread) begin
60 out_d <= { 1'b0, ddr2_read_data[36:0] };
62 end else if (!out_r && !out_a && inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !ddr2_addr_r && !ddr2_addr_a) begin
65 end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a && !ddr2_addr_r && !ddr2_addr_a) begin
73 == Test ========================================================
76 == Constants ========================================================
78 == Contributors =========================================================
79 Adam Megacz <megacz@cs.berkeley.edu>