3 == Ports ===========================================================
15 == TeX ==============================================================
17 {\tt Alu2} is a ``two-input'' arithmetic logic unit. It includes
18 logic for performing arithmetic operations on a pair of arguments.
19 Currently this includes
21 subtraction ({\sc sub}),
22 maximum ({\sc max}), and
25 \subsection*{Semantics}
27 When a value is present at each of {\tt in1}, {\tt in2} and {\tt
28 inOp}, these three values are consumed. Based on the value consumed
29 at {\tt inOp}, the requested operation is performed on the values
30 consumed from {\tt in1} and {\tt in2}. The result of this operation
31 is then made available at {\tt out}.
35 The {\it link bit} and other features of \cite{ies31} are not yet
38 The carry-in, carry-out, zero-test, negative-test, and overflow-test
39 flags typically present in a conventional processor ALU are also not
42 == Fleeterpreter ====================================================
43 public void service() {
44 if (box_in1.dataReadyForShip() &&
45 box_in2.dataReadyForShip() &&
46 box_inOp.dataReadyForShip() &&
47 box_out.readyForDataFromShip()) {
48 long a = box_in1.removeDataForShip();
49 long b = box_in2.removeDataForShip();
50 long op = box_inOp.removeDataForShip();
52 case 0: box_out.addDataFromShip(a+b); // ADD
54 case 1: box_out.addDataFromShip(a-b); // SUB
56 case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
58 case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
60 default: box_out.addDataFromShip(0);
66 == FleetSim ==============================================================
68 == FPGA ==============================================================
70 always @(posedge clk) begin
74 if (out_r && out_a) out_r <= 0;
75 if (!in1_r && in1_a) in1_a <= 0;
76 if (!in2_r && in2_a) in2_a <= 0;
77 if (!inOp_r && inOp_a) inOp_a <= 0;
78 if (!out_r && !out_a && in1_r && !in1_a && in2_r && !in2_a && inOp_r && !inOp_a) begin
84 0: out_d <= in1_d + in2_d;
85 1: out_d <= in1_d - in2_d;
86 2: out_d <= in1_d > in2_d ? in1_d : in2_d;
87 3: out_d <= in1_d > in2_d ? in2_d : in1_d;
94 == Test ==============================================================================
104 debug.in: [*] take, deliver;
106 literal 9; load repeat counter with 4; deliver;
109 literal 8; load repeat counter with 4; deliver;
112 literal Alu2.inOp[ADD]; deliver;
113 literal Alu2.inOp[SUB]; deliver;
114 literal Alu2.inOp[MIN]; deliver;
115 literal Alu2.inOp[MAX]; deliver;
117 alu.in1: [*] take, deliver;
118 alu.in2: [*] take, deliver;
119 alu.out: [*] take, sendto debug.in;
123 == Contributors =========================================================
124 Adam Megacz <megacz@cs.berkeley.edu>