3 == Ports ===========================================================
18 == TeX ==============================================================
20 {\tt Alu2} is a ``two-input'' arithmetic logic unit. It includes
21 logic for performing arithmetic operations on a pair of arguments.
22 Currently this includes
24 subtraction ({\sc sub}),
25 maximum ({\sc max}), and
28 \subsection*{Semantics}
30 When a value is present at each of {\tt in1}, {\tt in2} and {\tt
31 inOp}, these three values are consumed. Based on the value consumed
32 at {\tt inOp}, the requested operation is performed on the values
33 consumed from {\tt in1} and {\tt in2}. The result of this operation
34 is then made available at {\tt out}.
43 MAX - 0 if in1>in2, else 1
44 MIN - 1 if in1>in2, else 0
45 CMP - 0 if in1!=in2, else 1
50 The {\it link bit} and other features of \cite{ies31} are not yet
53 The carry-in, carry-out, zero-test, negative-test, and overflow-test
54 flags typically present in a conventional processor ALU are also not
57 == Fleeterpreter ====================================================
58 public void service() {
59 if (box_in1.dataReadyForShip() &&
60 box_in2.dataReadyForShip() &&
61 box_inOp.dataReadyForShip() &&
62 box_out.readyForDataFromShip()) {
63 long a = box_in1.removeDataForShip();
64 long b = box_in2.removeDataForShip();
65 long op = box_inOp.removeDataForShip();
67 case 0: box_out.addDataFromShip(a); // IN1
69 case 1: box_out.addDataFromShip(b); // IN2
71 case 2: box_out.addDataFromShip(a+b); // ADD
73 case 3: box_out.addDataFromShip(a-b); // SUB
75 case 4: box_out.addDataFromShip(Math.max(a,b)); // MAX
76 box_out.flag_c = !(a>b);
78 case 5: box_out.addDataFromShip(Math.min(a,b)); // MIN
81 default: box_out.addDataFromShip(0);
87 == FleetSim ==============================================================
89 == FPGA ==============================================================
91 wire [`DATAWIDTH:0] sum;
93 wire [(`DATAWIDTH-1):0] in2_inverted;
95 wire [(`DATAWIDTH-1):0] res;
100 assign isplus = inOp_d[2:0]==2;
101 assign cin = isplus ? 0 : 1;
102 assign in2_inverted = isplus ? in2_d : ~in2_d;
103 assign sum = {in1_d,cin} + {in2_inverted,cin};
104 assign res = sum[`DATAWIDTH:1];
105 assign greater = !res[`DATAWIDTH-1];
106 assign eq = in1_d == in2_d;
107 assign cout = sum[`DATAWIDTH];
109 assign out_d_[`DATAWIDTH] =
114 (inOp_d==4) ? ~greater :
115 (inOp_d==5) ? greater :
119 assign out_d_[(`DATAWIDTH-1):0] =
120 (inOp_d==0) ? (in1_d) :
121 (inOp_d==1) ? (in2_d) :
122 (inOp_d==2) ? (res) :
123 (inOp_d==3) ? (res) :
124 (inOp_d==4) ? (greater ? in1_d : in2_d) :
125 (inOp_d==5) ? (greater ? in2_d : in1_d) :
126 (inOp_d==6) ? {{ (`DATAWIDTH-1) {1'b0 }}, eq } :
129 always @(posedge clk) begin
133 if (!in1_r && in1_a) in1_a <= 0;
134 if (!in2_r && in2_a) in2_a <= 0;
135 if (!inOp_r && inOp_a) inOp_a <= 0;
136 if (out_r && out_a) begin
142 if (!out_r && !out_a && in1_r && !in1_a && in2_r && !in2_a && inOp_r && !inOp_a) begin
148 == Test ==============================================================================
150 // FIXME: need test for ADD carry-out c-flag
168 debug.in: set ilc=*; recv, deliver;
185 collect, send to debug.in;
187 set word= Alu2.inOp[ADD]; deliver;
188 set word= Alu2.inOp[SUB]; deliver;
189 set word= Alu2.inOp[IN1]; deliver;
190 set word= Alu2.inOp[IN2]; deliver;
193 set word= Alu2.inOp[MIN]; deliver;
194 set word= Alu2.inOp[MAX]; deliver;
195 set word= Alu2.inOp[CMP]; deliver;
196 set word= Alu2.inOp[CMP]; deliver;
199 collect, send to debug.in; // MIN
205 collect, send to debug.in; // MAX
211 collect, send to debug.in; // CMP
217 collect, send to debug.in; // CMP
223 == Contributors =========================================================
224 Adam Megacz <megacz@cs.berkeley.edu>