3 == Ports ===========================================================
10 == Constants ========================================================
11 ADD: add the two arguments; treat link as carry
12 SUB: subtract the two arguments; treat link as carry
16 == TeX ==============================================================
17 This ship is a two-input arithmetic unit. It features several
18 opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
21 FIXME: implement all the link bit stuff
23 Use carry-in bit to create a selector? Perhaps a waste of an ALU.
25 Flags: zero, negative, overflow, ?
34 == Fleeterpreter ====================================================
35 public long resolveLiteral(String literal) {
36 if (literal.equals("ADD")) return 0;
37 if (literal.equals("SUB")) return 1;
38 if (literal.equals("MAX")) return 2;
39 if (literal.equals("MIN")) return 3;
40 return super.resolveLiteral(literal);
42 public void service() {
43 if (box_in1.dataReadyForShip() &&
44 box_in2.dataReadyForShip() &&
45 box_inOp.dataReadyForShip() &&
46 box_out.readyForDataFromShip()) {
47 long a = box_in1.removeDataForShip();
48 long b = box_in2.removeDataForShip();
49 long op = box_inOp.removeDataForShip();
51 case 0: box_out.addDataFromShip(a+b); // ADD
53 case 1: box_out.addDataFromShip(a-b); // SUB
55 case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
57 case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
59 default: box_out.addDataFromShip(0);
65 == FleetSim ==============================================================
67 == FPGA ==============================================================
70 reg [(`DATAWIDTH-1):0] reg_a;
72 reg [(`DATAWIDTH-1):0] reg_b;
74 reg [(`DATAWIDTH-1):0] reg_op;
76 always @(posedge clk) begin
78 `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
81 `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
84 `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
87 if (have_a && have_b && have_op) begin
89 0: out_d = reg_a + reg_b;
90 1: out_d = reg_a - reg_b;
91 2: out_d = reg_a > reg_b ? reg_a : reg_b;
92 3: out_d = reg_a > reg_b ? reg_b : reg_a;
95 `onwrite(out_r, out_a)
106 == Contributors =========================================================
107 Adam Megacz <megacz@cs.berkeley.edu>