3 == Ports ===========================================================
10 == Constants ========================================================
11 ADD: add the two arguments; treat link as carry
12 SUB: subtract the two arguments; treat link as carry
19 SORT: output min(in1,in2) followed by max(in1,in2) (FIXME: redundant?)
21 == TeX ==============================================================
22 This ship is a two-input arithmetic unit. It features several
23 opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
26 FIXME: implement all the link bit stuff
28 Use carry-in bit to create a selector? Perhaps a waste of an ALU.
30 Carry-save / carry completion stuff.
32 Flags: zero, negative, overflow, ?
34 == Fleeterpreter ====================================================
35 public void service() {
36 if (box_in1.dataReadyForShip() &&
37 box_in2.dataReadyForShip() &&
38 box_inOp.dataReadyForShip() &&
39 box_out.readyForItemFromShip()) {
40 int a = box_in1.removeDataForShip();
41 int b = box_in2.removeDataForShip();
42 int op = box_inOp.removeDataForShip();
44 case 0: box_out.addDataFromShip(a+b); // ADD
46 case 1: box_out.addDataFromShip(a-b); // SUB
48 case 2: box_out.addDataFromShip(a*b); // MUL
50 case 3: box_out.addDataFromShip(a/b); // DIV
52 case 4: box_out.addDataFromShip(a%b); // REM
54 default: box_out.addDataFromShip(0);
60 == FleetSim ==============================================================
62 == FPGA ==============================================================
65 `input(in1_r, in1_a, in1_a_, [(`DATAWIDTH-1):0], in1_d)
66 `input(in2_r, in2_a, in2_a_, [(`DATAWIDTH-1):0], in2_d)
67 `input(inOp_r, inOp_a, inOp_a_, [(`DATAWIDTH-1):0], inOp_d)
68 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
70 `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
73 reg [(`DATAWIDTH-1):0] reg_a;
75 reg [(`DATAWIDTH-1):0] reg_b;
77 reg [(`DATAWIDTH-1):0] reg_op;
79 always @(posedge clk) begin
81 `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
84 `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
87 `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
90 if (have_a && have_b && have_op) begin
92 0: out_d = reg_a + reg_b;
93 1: out_d = reg_a - reg_b;
94 //2: out_d = reg_a * reg_b; // will not synthesize --AM
95 //3: out_d = reg_a / reg_b; // will not synthesize --AM
96 //4: out_d = reg_a % reg_b; // will not synthesize --AM
99 `onwrite(out_r, out_a)
111 == Contributors =========================================================
112 Adam Megacz <megacz@cs.berkeley.edu>