3 == Ports ===========================================================
15 == TeX ==============================================================
17 {\tt Alu2} is a ``two-input'' arithmetic logic unit. It includes
18 logic for performing arithmetic operations on a pair of arguments.
19 Currently this includes
21 subtraction ({\sc sub}),
22 maximum ({\sc max}), and
25 \subsection*{Semantics}
27 When a value is present at each of {\tt in1}, {\tt in2} and {\tt
28 inOp}, these three values are consumed. Based on the value consumed
29 at {\tt inOp}, the requested operation is performed on the values
30 consumed from {\tt in1} and {\tt in2}. The result of this operation
31 is then made available at {\tt out}.
35 The {\it link bit} and other features of \cite{ies31} are not yet
38 The carry-in, carry-out, zero-test, negative-test, and overflow-test
39 flags typically present in a conventional processor ALU are also not
42 == Fleeterpreter ====================================================
43 public long resolveLiteral(String literal) {
44 if (literal.equals("ADD")) return 0;
45 if (literal.equals("SUB")) return 1;
46 if (literal.equals("MAX")) return 2;
47 if (literal.equals("MIN")) return 3;
48 return super.resolveLiteral(literal);
50 public void service() {
51 if (box_in1.dataReadyForShip() &&
52 box_in2.dataReadyForShip() &&
53 box_inOp.dataReadyForShip() &&
54 box_out.readyForDataFromShip()) {
55 long a = box_in1.removeDataForShip();
56 long b = box_in2.removeDataForShip();
57 long op = box_inOp.removeDataForShip();
59 case 0: box_out.addDataFromShip(a+b); // ADD
61 case 1: box_out.addDataFromShip(a-b); // SUB
63 case 2: box_out.addDataFromShip(Math.max(a,b)); // MAX
65 case 3: box_out.addDataFromShip(Math.min(a,b)); // MIN
67 default: box_out.addDataFromShip(0);
73 == FleetSim ==============================================================
75 == FPGA ==============================================================
78 reg [(`DATAWIDTH-1):0] reg_a;
80 reg [(`DATAWIDTH-1):0] reg_b;
82 reg [(`DATAWIDTH-1):0] reg_op;
84 always @(posedge clk) begin
86 `onread(in1_r, in1_a) have_a = 1; reg_a = in1_d; end
89 `onread(in2_r, in2_a) have_b = 1; reg_b = in2_d; end
92 `onread(inOp_r, inOp_a) have_op = 1; reg_op = inOp_d; end
95 if (have_a && have_b && have_op) begin
97 0: out_d = reg_a + reg_b;
98 1: out_d = reg_a - reg_b;
99 2: out_d = reg_a > reg_b ? reg_a : reg_b;
100 3: out_d = reg_a > reg_b ? reg_b : reg_a;
103 `onwrite(out_r, out_a)
111 == Test ==============================================================================
121 debug.in: [*] take, deliver;
123 literal 9; load repeat counter with 4; deliver;
126 literal 8; load repeat counter with 4; deliver;
128 alu.in1: [*] take, deliver;
129 alu.in2: [*] take, deliver;
130 alu.out: [*] take, sendto debug.in;
133 literal Alu2.inOp[ADD]; deliver;
134 literal Alu2.inOp[SUB]; deliver;
135 literal Alu2.inOp[MIN]; deliver;
136 literal Alu2.inOp[MAX]; deliver;
140 == Contributors =========================================================
141 Adam Megacz <megacz@cs.berkeley.edu>