3 == Ports ===========================================================
10 == Constants ========================================================
11 ADD: add the two arguments; treat link as carry
12 SUB: subtract the two arguments; treat link as carry
19 SORT: output min(in1,in2) followed by max(in1,in2) (FIXME: redundant?)
21 == TeX ==============================================================
22 This ship is a two-input arithmetic unit. It features several
23 opcodes, such as {\tt ADD} and {\tt SUB}. In my opinion, it is
26 FIXME: implement all the link bit stuff
28 Use carry-in bit to create a selector? Perhaps a waste of an ALU.
30 Carry-save / carry completion stuff.
32 Flags: zero, negative, overflow, ?
34 == Fleeterpreter ====================================================
35 public void service() {
36 if (box_in1.dataReadyForShip() &&
37 box_in2.dataReadyForShip() &&
38 box_inOp.dataReadyForShip() &&
39 box_out.readyForItemFromShip()) {
40 int a = box_in1.removeDataForShip();
41 int b = box_in2.removeDataForShip();
42 int op = box_inOp.removeDataForShip();
44 case 0: box_out.addDataFromShip(a+b); // ADD
46 case 1: box_out.addDataFromShip(a-b); // SUB
48 case 2: box_out.addDataFromShip(a*b); // MUL
50 case 3: box_out.addDataFromShip(a/b); // DIV
52 case 4: box_out.addDataFromShip(a%b); // REM
54 default: box_out.addDataFromShip(0);
60 == FleetSim ==============================================================
62 == FPGA ==============================================================
69 out_r_, out_a, out_d_);
72 `input(a_r, a_a, a_a_, [(`DATAWIDTH-1):0], a_d)
73 `input(b_r, b_a, b_a_, [(`DATAWIDTH-1):0], b_d)
74 `input(op_r, op_a, op_a_, [(`DATAWIDTH-1):0], op_d)
75 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
76 `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
79 reg [(`DATAWIDTH-1):0] reg_a;
81 reg [(`DATAWIDTH-1):0] reg_b;
83 reg [(`DATAWIDTH-1):0] reg_op;
85 always @(posedge clk) begin
87 `onread(a_r, a_a) have_a = 1; reg_a = a_d; end
90 `onread(b_r, b_a) have_b = 1; reg_b = b_d; end
93 `onread(op_r, op_a) have_op = 1; reg_op = op_d; end
96 if (have_a && have_b && have_op) begin
98 0: out_d = reg_a + reg_b;
99 1: out_d = reg_a - reg_b;
100 //2: out_d = reg_a * reg_b; // will not synthesize --AM
101 //3: out_d = reg_a / reg_b; // will not synthesize --AM
102 //4: out_d = reg_a % reg_b; // will not synthesize --AM
105 `onwrite(out_r, out_a)
117 == Contributors =========================================================
118 Adam Megacz <megacz@cs.berkeley.edu>