ships/Alu3.ship

   1 ship: Alu3
   2
   3 == Ports ===========================================================
   4 data  in:   in1
   5 data  in:   in2
   6 data  in:   in3
   7
   8 data  out:  out1
   9   shortcut to: in1
  10 data  out:  out2
  11   shortcut to: in2
  12 data  out:  out3
  13   shortcut to: in3
  14 data  out:  outBits
  15
  16 == Constants ========================================================
  17 == TeX ==============================================================
  18
  19 == Fleeterpreter ====================================================
  20 boolean mode = false;
  21 BitFifo.BitStorage outBits = new BitFifo.BitStorage(74);
  22 public void service() {
  23   if (outBits.size() >= 37) {
  24     if (box_outBits.readyForDataFromShip()) {
  25         box_outBits.addDataFromShip(outBits.get(37));
  26     }
  27   } else
  28   if (box_in1.dataReadyForShip() &&
  29       box_in2.dataReadyForShip() &&
  30       box_in3.dataReadyForShip() &&
  31       outBits.hasSpace(1) &&
  32       box_out1.readyForDataFromShip() &&
  33       box_out2.readyForDataFromShip() &&
  34       box_out3.readyForDataFromShip()) {
  35       long v1 = box_in1.removeDataForShip();
  36       long v2 = box_in2.removeDataForShip();
  37       long v3 = box_in3.removeDataForShip();
  38       long o1, o2, o3;
  39       o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
  40       o2 = (v1 ^ v2 ^ v3) >> 1;
  41       o3 = 0;
  42       outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
  43       box_out1.addDataFromShip(o1);
  44       box_out2.addDataFromShip(o2);
  45       box_out3.addDataFromShip(o3);
  46   }
  47 }
  48
  49 == FleetSim ==============================================================
  50
  51 == FPGA ==============================================================
  52
  53   reg                    mode;         initial mode = 0;
  54   reg                    have_in1;     initial have_in1 = 0;
  55   reg                    have_in2;     initial have_in2 = 0;
  56   reg                    have_in3;     initial have_in3 = 0;
  57   reg [(`DATAWIDTH-1):0] keep_in1;     initial keep_in1 = 0;
  58   reg [(`DATAWIDTH-1):0] keep_in2;     initial keep_in2 = 0;
  59   reg [(`DATAWIDTH-1):0] keep_in3;     initial keep_in3 = 0;
  60   reg                    have_out1;    initial have_out1 = 0;
  61   reg                    have_out2;    initial have_out2 = 0;
  62   reg                    have_out3;    initial have_out3 = 0;
  63   reg [73:0] bitstorage; initial bitstorage = 0;
  64   reg [7:0] bitstorage_count;          initial bitstorage_count = 0;
  65   reg wrote;                           initial wrote = 0;
  66
  67   always @(posedge clk) begin
  68     wrote = 0;
  69     if (have_out1) begin
  70       `onwrite(out1_r, out1_a) have_out1 <= 0; end
  71     end else if (have_out2) begin
  72       `onwrite(out2_r, out2_a) have_out2 <= 0; end
  73     end else if (have_out3) begin
  74       `onwrite(out3_r, out3_a) have_out3 <= 0; end
  75     end else if (!have_in1) begin
  76       `onread(in1_r, in1_a) have_in1 <= 1; keep_in1 <= in1_d; end
  77     end else if (!have_in2) begin
  78       `onread(in2_r, in2_a) have_in2 <= 1; keep_in2 <= in2_d; end
  79     end else if (!have_in3) begin
  80       `onread(in3_r, in3_a) have_in3 <= 1; keep_in3 <= in3_d; end
  81     end else if (bitstorage_count >= `DATAWIDTH) begin
  82       outBits_d  = bitstorage[(`DATAWIDTH-1):0];
  83       `onwrite(outBits_r, outBits_a)
  84         bitstorage_count <= 0;
  85       end
  86     end else begin
  87           out1_d           <= { ((keep_in1 & keep_in2) | (keep_in2 & keep_in3) | (keep_in1 & keep_in3)) };
  88           out2_d                       <= { 1'b0, (keep_in1[(`DATAWIDTH-1):1] ^
  89                                                    keep_in2[(`DATAWIDTH-1):1] ^
  90                                                    keep_in3[(`DATAWIDTH-1):1]) };
  91           out3_d                       <= 0;
  92           bitstorage[bitstorage_count]  = (keep_in1[0] ^ keep_in2[0] ^ keep_in3[0]);
  93           bitstorage_count             <= bitstorage_count+1;
  94         have_out1 <= 1;
  95         have_out2 <= 1;
  96         have_out3 <= 1;
  97         have_in1  <= 0;
  98         have_in2  <= 0;
  99         have_in3  <= 0;
 100     end
 101
 102   end
 103
 104
 105
 106 == Test ========================================================================
 107
 108 #ship alu3    : Alu3
 109 #ship lut3    : Lut3
 110 #ship bitfifo : BitFifo
 111 #ship debug   : Debug
 112
 113 #expect 31509911677
 114 #expect 1855678
 115
 116 // 0:  100100100111110000000
 117 // sel 011110100001001000000
 118 // 1:  111000101000011000011
 119 // r:  111000100110111000000
 120
 121 1000000:            sendto bitfifo.inEnqueue;
 122 0:                  sendto bitfifo.inEnqueue;
 123 bitfifo.inEnqueue:  [*] take, deliver;
 124 bitfifo.outDequeue: [*] wait, take, sendto lut3.in2;
 125 lut3.in2:           notify bitfifo.outDequeue;
 126                     [74] take, deliver, notify bitfifo.outDequeue;
 127
 128 // mux on second input
 129 226:                sendto lut3.inLut;
 130 lut3.inLut:         take;
 131                     [74] deliver;
 132
 133 1855683:            sendto lut3.in1;
 134 0:                  sendto lut3.in1;
 135 lut3.in1:           take;
 136                     [37] deliver;
 137                     take;
 138                     [37] deliver;
 139
 140 1200000:            sendto lut3.in3;
 141 0:                  sendto lut3.in3;
 142 lut3.in3:           take;
 143                     [37] deliver;
 144                     take;
 145                     [37] deliver;
 146
 147 lut3.out:           [*] take, sendto alu3.in2;
 148
 149 0:             sendto alu3.in3;
 150 0:             sendto alu3.in1;
 151 alu3.in1:      [*] take, deliver;
 152 alu3.in2:      [*] take, deliver;
 153 alu3.in3:      [*] take, deliver;
 154 alu3.out1:     [74] take, sendto alu3.in1;
 155 alu3.out2:     [74] take, sendto alu3.in3;
 156 alu3.out3:     [74] take;
 157 alu3.outBits:  [*] take, sendto debug.in;
 158
 159
 160 debug.in:      [*] take, deliver;
 161
 162
 163 == Contributors =========================================================
 164 Amir Kamil <kamil@cs.berkeley.edu>
 165 Adam Megacz <megacz@cs.berkeley.edu>