3 == Ports ===========================================================
16 == Constants ========================================================
17 == TeX ==============================================================
19 == Fleeterpreter ====================================================
21 BitFifo.BitStorage outBits = new BitFifo.BitStorage(74);
22 public void service() {
23 if (box_in1.dataReadyForShip() &&
24 box_in2.dataReadyForShip() &&
25 box_in3.dataReadyForShip() &&
26 outBits.hasSpace(1) &&
27 box_out1.readyForDataFromShip() &&
28 box_out2.readyForDataFromShip() &&
29 box_out3.readyForDataFromShip()) {
30 long v1 = box_in1.removeDataForShip();
31 long v2 = box_in2.removeDataForShip();
32 long v3 = box_in3.removeDataForShip();
38 o3 = ((v2 & 0x1L) == 0) ? 0 : v1;
40 o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
41 o2 = (v1 ^ v2 ^ v3) >> 1;
43 outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
45 box_out1.addDataFromShip(o1);
46 box_out2.addDataFromShip(o2);
47 box_out3.addDataFromShip(o3);
51 if (box_outBits.readyForDataFromShip() &&
52 outBits.size() >= 37) {
53 box_outBits.addDataFromShip(outBits.get(37));
57 == FleetSim ==============================================================
59 == FPGA ==============================================================
61 reg mode; initial mode = 0;
62 reg have_in1; initial have_in1 = 0;
63 reg have_in2; initial have_in2 = 0;
64 reg have_in3; initial have_in3 = 0;
65 reg [(`DATAWIDTH-1):0] keep_in1; initial keep_in1 = 0;
66 reg [(`DATAWIDTH-1):0] keep_in2; initial keep_in2 = 0;
67 reg [(`DATAWIDTH-1):0] keep_in3; initial keep_in3 = 0;
68 reg have_out1; initial have_out1 = 0;
69 reg have_out2; initial have_out2 = 0;
70 reg have_out3; initial have_out3 = 0;
71 reg [73:0] bitstorage;
72 reg [7:0] bitstorage_count; initial bitstorage_count = 0;
73 reg wrote; initial wrote = 0;
75 always @(posedge clk) begin
78 `onwrite(out1_r, out1_a) have_out1 <= 0; end
79 end else if (have_out2) begin
80 `onwrite(out2_r, out2_a) have_out2 <= 0; end
81 end else if (have_out3) begin
82 `onwrite(out3_r, out3_a) have_out3 <= 0; end
83 end else if (!have_in1) begin
84 `onread(in1_r, in1_a) have_in1 <= 1; keep_in1 <= in1_d; end
85 end else if (!have_in2) begin
86 `onread(in2_r, in2_a) have_in2 <= 1; keep_in2 <= in2_d; end
87 end else if (!have_in3) begin
88 `onread(in3_r, in3_a) have_in3 <= 1; keep_in3 <= in3_d; end
93 out2_d <= { 1'b0, keep_in2[(`DATAWIDTH-1):1] };
94 out3_d <= (keep_in2[0]==0) ? 0 : keep_in1;
96 out1_d <= { ((keep_in1 & keep_in2) | (keep_in2 & keep_in3) | (keep_in1 & keep_in3)) };
97 out2_d <= (keep_in1 ^ keep_in2 ^ keep_in3) >> 1;
99 bitstorage_count <= bitstorage_count+1;
100 bitstorage[bitstorage_count] = (keep_in1[0] ^ keep_in2[0] ^ keep_in3[0]);
101 outBits_d = bitstorage[(`DATAWIDTH-1):0];
113 if (!wrote && bitstorage_count >= `DATAWIDTH) begin
114 `onwrite(outBits_r, outBits_a) begin
115 bitstorage_count <= bitstorage_count - `DATAWIDTH;
116 bitstorage = bitstorage >> `DATAWIDTH;
123 == Test ========================================================================
131 1000000: sendto alu3.in1;
132 1200000: sendto alu3.in2;
136 alu3.in1: [*] take, deliver;
137 alu3.in2: [*] take, deliver;
138 alu3.in3: [*] take, deliver;
139 alu3.out1: [74] take, sendto alu3.in1;
140 [74] take, sendto alu3.in1;
141 alu3.out2: [74] take, sendto alu3.in2;
142 [74] take, sendto alu3.in2;
143 alu3.out3: [74] take, sendto alu3.in3;
144 [74] take, sendto alu3.in3;
145 alu3.outBits: [2] take, sendto debug.in;
146 debug.in: [*] take, deliver;
149 == Contributors =========================================================
150 Amir Kamil <kamil@cs.berkeley.edu>
151 Adam Megacz <megacz@cs.berkeley.edu>