ships/Alu3.ship

   1 ship: Alu3
   2
   3 == Ports ===========================================================
   4 data  in:   in1
   5 data  in:   in2
   6 data  in:   in3
   7
   8 data  out:  out1
   9   shortcut to: in1
  10 data  out:  out2
  11   shortcut to: in2
  12 data  out:  out3
  13   shortcut to: in3
  14 data  out:  outBits
  15
  16 == Constants ========================================================
  17 == TeX ==============================================================
  18
  19 == Fleeterpreter ====================================================
  20 boolean mode = false;
  21 BitFifo.BitStorage outBits = new BitFifo.BitStorage(74);
  22 public void service() {
  23   if (box_in1.dataReadyForShip() &&
  24       box_in2.dataReadyForShip() &&
  25       box_in3.dataReadyForShip() &&
  26       outBits.hasSpace(1) &&
  27       box_out1.readyForDataFromShip() &&
  28       box_out2.readyForDataFromShip() &&
  29       box_out3.readyForDataFromShip()) {
  30       long v1 = box_in1.removeDataForShip();
  31       long v2 = box_in2.removeDataForShip();
  32       long v3 = box_in3.removeDataForShip();
  33       long o1, o2, o3;
  34       mode = true;
  35       if (!mode) {
  36         o1 = v1;
  37         o2 = v2 >>> 1;
  38         o3 = ((v2 & 0x1L) == 0) ? 0 : v1;
  39       } else {
  40         o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
  41         o2 = (v1 ^ v2 ^ v3) >> 1;
  42         o3 = 0;
  43         outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
  44       }
  45       box_out1.addDataFromShip(o1);
  46       box_out2.addDataFromShip(o2);
  47       box_out3.addDataFromShip(o3);
  48       mode = !mode;
  49   }
  50
  51   if (box_outBits.readyForDataFromShip() &&
  52       outBits.size() >= 37) {
  53       box_outBits.addDataFromShip(outBits.get(37));
  54   }
  55 }
  56
  57 == FleetSim ==============================================================
  58
  59 == FPGA ==============================================================
  60
  61   reg                    mode;         initial mode = 0;
  62   reg                    have_in1;     initial have_in1 = 0;
  63   reg                    have_in2;     initial have_in2 = 0;
  64   reg                    have_in3;     initial have_in3 = 0;
  65   reg [(`DATAWIDTH-1):0] keep_in1;     initial keep_in1 = 0;
  66   reg [(`DATAWIDTH-1):0] keep_in2;     initial keep_in2 = 0;
  67   reg [(`DATAWIDTH-1):0] keep_in3;     initial keep_in3 = 0;
  68   reg                    have_out1;    initial have_out1 = 0;
  69   reg                    have_out2;    initial have_out2 = 0;
  70   reg                    have_out3;    initial have_out3 = 0;
  71   reg [73:0] bitstorage;
  72   reg [7:0] bitstorage_count;          initial bitstorage_count = 0;
  73   reg wrote;                           initial wrote = 0;
  74
  75   always @(posedge clk) begin
  76     wrote = 0;
  77     if (have_out1) begin
  78       `onwrite(out1_r, out1_a) have_out1 <= 0; end
  79     end else if (have_out2) begin
  80       `onwrite(out2_r, out2_a) have_out2 <= 0; end
  81     end else if (have_out3) begin
  82       `onwrite(out3_r, out3_a) have_out3 <= 0; end
  83     end else if (!have_in1) begin
  84       `onread(in1_r, in1_a) have_in1 <= 1; keep_in1 <= in1_d; end
  85     end else if (!have_in2) begin
  86       `onread(in2_r, in2_a) have_in2 <= 1; keep_in2 <= in2_d; end
  87     end else if (!have_in3) begin
  88       `onread(in3_r, in3_a) have_in3 <= 1; keep_in3 <= in3_d; end
  89     end else begin
  90         mode = 1;
  91         if (mode == 0) begin
  92           out1_d    <= keep_in1;
  93           out2_d    <= { 1'b0, keep_in2[(`DATAWIDTH-1):1] };
  94           out3_d    <= (keep_in2[0]==0) ? 0 : keep_in1;
  95         end else begin
  96           out1_d           <= { ((keep_in1 & keep_in2) | (keep_in2 & keep_in3) | (keep_in1 & keep_in3)) };
  97           out2_d                       <= (keep_in1 ^ keep_in2 ^ keep_in3) >> 1;
  98           out3_d                       <= 0;
  99           bitstorage_count             <= bitstorage_count+1;
 100           bitstorage[bitstorage_count] = (keep_in1[0] ^ keep_in2[0] ^ keep_in3[0]);
 101           outBits_d                    = bitstorage[(`DATAWIDTH-1):0];
 102           wrote = 1;
 103         end
 104         have_out1 <= 1;
 105         have_out2 <= 1;
 106         have_out3 <= 1;
 107         have_in1  <= 0;
 108         have_in2  <= 0;
 109         have_in3  <= 0;
 110 //        mode <= ~mode;
 111     end
 112
 113     if (!wrote && bitstorage_count >= `DATAWIDTH) begin
 114       `onwrite(outBits_r, outBits_a) begin
 115         bitstorage_count <= bitstorage_count - `DATAWIDTH;
 116         bitstorage       = bitstorage >> `DATAWIDTH;
 117       end
 118     end
 119   end
 120 end
 121
 122
 123 == Test ========================================================================
 124
 125 #ship alu3    : Alu3
 126 #ship lut3    : Lut3
 127 #ship bitfifo : BitFifo
 128 #ship debug   : Debug
 129
 130 #expect 31509911677
 131 #expect 1855678
 132
 133 //#expect 1855683
 134 //#expect 1855683
 135 //#expect 1855683
 136 //#expect 1855683
 137 //#expect 1855683
 138 //#expect 1855683
 139 //#expect 1200000
 140 //#expect 1855683
 141 //#expect 1855683
 142 //#expect 1200000
 143 //#expect 1855683
 144 //#expect 1855683
 145 //#expect 1855683
 146 //#expect 1855683
 147 //#expect 1200000
 148 //#expect 1855683
 149 //#expect 1200000
 150 //#expect 1200000
 151 //#expect 1200000
 152 //#expect 1200000
 153 //#expect 1855683
 154
 155 // 0:  100100100111110000000
 156 // sel 011110100001001000000
 157 // 1:  111000101000011000011
 158 // r:  111000100110111000000
 159
 160
 161 1000000:            sendto bitfifo.inEnqueue;
 162 0:                  sendto bitfifo.inEnqueue;
 163 bitfifo.inEnqueue:  [*] take, deliver;
 164 bitfifo.outDequeue: [*] take, sendto lut3.in2;
 165 lut3.in2:           [74] take, deliver;
 166
 167 // mux on second input
 168 226:                sendto lut3.inLut;
 169 lut3.inLut:         take;
 170                     [74] deliver;
 171
 172 1855683:            sendto lut3.in1;
 173 0:                  sendto lut3.in1;
 174 lut3.in1:           take;
 175                     [37] deliver;
 176                     take;
 177                     [37] deliver;
 178
 179 1200000:            sendto lut3.in3;
 180 0:                  sendto lut3.in3;
 181 lut3.in3:           take;
 182                     [37] deliver;
 183                     take;
 184                     [37] deliver;
 185
 186 lut3.out:           [*] take, sendto alu3.in2;
 187
 188
 189 0:             sendto alu3.in3;
 190 0:             sendto alu3.in1;
 191 alu3.in1:      [*] take, deliver;
 192 alu3.in2:      [*] take, deliver;
 193 alu3.in3:      [*] take, deliver;
 194 alu3.out1:     [74] take, sendto alu3.in1;
 195 alu3.out2:     [74] take, sendto alu3.in3;
 196 alu3.out3:     [74] take;
 197 alu3.outBits:  [2] take, sendto debug.in;
 198
 199
 200 debug.in:           [*] take, deliver;
 201
 202
 203 == Contributors =========================================================
 204 Amir Kamil <kamil@cs.berkeley.edu>
 205 Adam Megacz <megacz@cs.berkeley.edu>