ships/Alu3.ship

   1 ship: Alu3
   2
   3 == Ports ===========================================================
   4 data  in:   in1
   5 data  in:   in2
   6 data  in:   in3
   7
   8 data  out:  out1
   9   shortcut to: in1
  10 data  out:  out2
  11   shortcut to: in2
  12 data  out:  out3
  13   shortcut to: in3
  14 data  out:  outBits
  15
  16 == Constants ========================================================
  17 == TeX ==============================================================
  18
  19 == Fleeterpreter ====================================================
  20 boolean mode = false;
  21 BitFifo.BitStorage outBits = new BitFifo.BitStorage(74);
  22 public void service() {
  23   if (outBits.size() >= 37) {
  24     if (box_outBits.readyForDataFromShip()) {
  25         box_outBits.addDataFromShip(outBits.get(37));
  26     }
  27   } else
  28   if (box_in1.dataReadyForShip() &&
  29       box_in2.dataReadyForShip() &&
  30       box_in3.dataReadyForShip() &&
  31       outBits.hasSpace(1) &&
  32       box_out1.readyForDataFromShip() &&
  33       box_out2.readyForDataFromShip() &&
  34       box_out3.readyForDataFromShip()) {
  35       long v1 = box_in1.removeDataForShip();
  36       long v2 = box_in2.removeDataForShip();
  37       long v3 = box_in3.removeDataForShip();
  38       long o1, o2, o3;
  39       o1 = ((v1 & v2) | (v2 & v3) | (v1 & v3))/* << 1*/;
  40       o2 = (v1 ^ v2 ^ v3) >> 1;
  41       o3 = 0;
  42       outBits.add((v1 ^ v2 ^ v3) & 0x1L, 1);
  43       box_out1.addDataFromShip(o1);
  44       box_out2.addDataFromShip(o2);
  45       box_out3.addDataFromShip(o3);
  46   }
  47 }
  48
  49 == FleetSim ==============================================================
  50
  51 == FPGA ==============================================================
  52
  53   reg                    mode;         initial mode = 0;
  54   reg                    have_in1;     initial have_in1 = 0;
  55   reg                    have_in2;     initial have_in2 = 0;
  56   reg                    have_in3;     initial have_in3 = 0;
  57   reg [(`DATAWIDTH-1):0] keep_in1;     initial keep_in1 = 0;
  58   reg [(`DATAWIDTH-1):0] keep_in2;     initial keep_in2 = 0;
  59   reg [(`DATAWIDTH-1):0] keep_in3;     initial keep_in3 = 0;
  60   reg                    have_out1;    initial have_out1 = 0;
  61   reg                    have_out2;    initial have_out2 = 0;
  62   reg                    have_out3;    initial have_out3 = 0;
  63   reg [73:0] bitstorage; initial bitstorage = 0;
  64   reg [7:0] bitstorage_count;          initial bitstorage_count = 0;
  65   reg wrote;                           initial wrote = 0;
  66
  67   always @(posedge clk) begin
  68     wrote = 0;
  69     if (bitstorage_count >= `DATAWIDTH) begin
  70       outBits_d  = bitstorage[(`DATAWIDTH-1):0];
  71       `onwrite(outBits_r, outBits_a)
  72         bitstorage_count <= 0;
  73         bitstorage        = bitstorage >> `DATAWIDTH;
  74       end
  75     end else if (have_out1) begin
  76       `onwrite(out1_r, out1_a) have_out1 <= 0; end
  77     end else if (have_out2) begin
  78       `onwrite(out2_r, out2_a) have_out2 <= 0; end
  79     end else if (have_out3) begin
  80       `onwrite(out3_r, out3_a) have_out3 <= 0; end
  81     end else if (!have_in1) begin
  82       `onread(in1_r, in1_a) have_in1 <= 1; keep_in1 <= in1_d; end
  83     end else if (!have_in2) begin
  84       `onread(in2_r, in2_a) have_in2 <= 1; keep_in2 <= in2_d; end
  85     end else if (!have_in3) begin
  86       `onread(in3_r, in3_a) have_in3 <= 1; keep_in3 <= in3_d; end
  87     end else begin
  88           out1_d           <= { ((keep_in1 & keep_in2) | (keep_in2 & keep_in3) | (keep_in1 & keep_in3)) };
  89           out2_d                       <= { 1'b0, (keep_in1[(`DATAWIDTH-1):1] ^
  90                                                    keep_in2[(`DATAWIDTH-1):1] ^
  91                                                    keep_in3[(`DATAWIDTH-1):1]) };
  92           out3_d                       <= 0;
  93         bitstorage[bitstorage_count]  = (keep_in1[0] ^ keep_in2[0] ^ keep_in3[0]);
  94         bitstorage_count             <= bitstorage_count+1;
  95         have_out1 <= 1;
  96         have_out2 <= 1;
  97         have_out3 <= 1;
  98         have_in1  <= 0;
  99         have_in2  <= 0;
 100         have_in3  <= 0;
 101     end
 102
 103   end
 104
 105
 106
 107 == Test ========================================================================
 108
 109 #ship alu3    : Alu3
 110 #ship lut3    : Lut3
 111 #ship bitfifo : BitFifo
 112 #ship debug   : Debug
 113 #ship fifo    : Fifo
 114
 115 #expect -66848683
 116 #expect 18682
 117
 118 // 0:  100100100111110000000
 119 // sel 011110100001001000000
 120 // 1:  111000101000011000011
 121 // r:  111000100110111000000
 122
 123 bitfifo.in:
 124   deliver;      // deliver a junk word
 125   literal 10000;
 126   [37] deliver; // deliver it 37 times (once per bit)
 127   literal 0;
 128   [38] deliver; // deliver it 37 times
 129
 130 // insert bits in lsb order
 131 bitfifo.inOp:
 132   literal BitFifo.inOp[lsbFirst,take=37];
 133   [*] deliver;
 134
 135 // toss out 37 bits, take one, repeat.  sign extend the result
 136 bitfifo.outOp:
 137   literal BitFifo.outOp[drop=37,take=1,signExtend];
 138   [*] deliver;
 139
 140 bitfifo.out:        [*] wait, take, sendto lut3.in2;
 141 lut3.in2:           [4] notify bitfifo.out;
 142                     [74] take, deliver, notify bitfifo.out;
 143
 144 // mux on second input
 145 lut3.inLut:         literal 226;
 146                     [74] deliver;
 147
 148 lut3.in1:           literal 18683;
 149                     [37] deliver;
 150                     literal 0;
 151                     [37] deliver;
 152
 153 lut3.in3:           literal 12000;
 154                     [37] deliver;
 155                     literal 0;
 156                     [37] deliver;
 157
 158 lut3.out:           [*] wait, take, sendto alu3.in2;
 159
 160 alu3.in1:      literal 0; deliver; [*] take, deliver;
 161 alu3.in2:      [1] notify lut3.out; [*] take, deliver, notify lut3.out;
 162 alu3.in3:      literal 0; deliver; [*] take, deliver;
 163 alu3.out1:     [74] take, sendto alu3.in1;
 164 alu3.out2:     [74] take, sendto alu3.in3;
 165 alu3.out3:     [74] take;
 166 alu3.outBits:  [*] take, sendto debug.in;
 167
 168
 169 debug.in:      [*] take, deliver;
 170
 171
 172 == Contributors =========================================================
 173 Amir Kamil <kamil@cs.berkeley.edu>
 174 Adam Megacz <megacz@cs.berkeley.edu>