3 == Ports ===========================================================
7 data in: in.swapIfNonZero
8 data in: in.swapIfNegative
9 data in: in.swapIfPositive
10 data in: in.swapIfNonNegative
11 data in: in.swapIfNonPositive
13 data in: in.muxIfNonZero
14 data in: in.muxIfNegative
15 data in: in.muxIfPositive
16 data in: in.muxIfNonNegative
17 data in: in.muxIfNonPositive
18 data in: in.deMuxIfZero
19 data in: in.deMuxIfNonZero
20 data in: in.deMuxIfNegative
21 data in: in.deMuxIfPositive
22 data in: in.deMuxIfNonNegative
23 data in: in.deMuxIfNonPositive
28 == Constants ========================================================
30 == TeX ==============================================================
32 This ship needs to be updated to use opcode ports \cite{am25}. For a
33 general idea of what this ship is supposed to do, see \cite{am17}.
35 %With judicious programming of its pumps, this ship can be used to
36 %implement nearly all forms of selection and branching.
38 %When data is available at the in port, it is examined. Which
39 %destination the datum has arrived on determines the *condition* the
40 %datum should be tested for and the *action* which should be taken if
41 %the condition holds true.
43 %The latter portion of the name of the destination (IfZero,
44 %If(Non)Positive, If(Non)Negative) determines the condition which the
45 %datum on the in port is tested for. The former portion (mux, demux,
46 %swap) determines the *action* to be taken if the condition tests true.
49 % action condition effect
50 % ------ --------- -------------------------------
51 % swap false in1->out1 in2->out2
52 % swap true in2->out1 in1->out2
55 % demux false in1->out1
56 % demux true in1->out2
59 %In each case, the ship will wait for a datum to be available on all
60 %input ports (and only those ports) mentioned in the appropriate row of
61 %the "effect" column above, and will output them on the corresponding
65 == Fleeterpreter ====================================================
66 private Packet selector;
67 public void service() {
68 if (!box_out1.readyForDataFromShip() || !box_out2.readyForDataFromShip()) return;
69 if (selector == null && !box_in.dataReadyForShip()) return;
70 if (selector == null) selector = box_in.removePacketForShip();
71 String port = selector.destination.getDestinationName();
73 if (port.startsWith("swap") && (!box_in1.dataReadyForShip() || !box_in2.dataReadyForShip())) return;
74 if (port.startsWith("mux") && (!box_in1.dataReadyForShip() || !box_in2.dataReadyForShip())) return;
75 if (port.startsWith("deMux") && (!box_in1.dataReadyForShip())) return;
77 long val = selector.value;
78 boolean condition = false;
79 if (port.endsWith("IfZero")) condition = val==0;
80 if (port.endsWith("IfNonZero")) condition = val!=0;
81 if (port.endsWith("IfPositive")) condition = val>0;
82 if (port.endsWith("IfNegative")) condition = val<0;
83 if (port.endsWith("IfNonPositive")) condition = val<=0;
84 if (port.endsWith("IfNonNegative")) condition = val>=0;
85 if (port.startsWith("swap")) {
87 box_out1.addDataFromShip(box_in2.removeDataForShip());
88 box_out2.addDataFromShip(box_in1.removeDataForShip());
91 box_out1.addDataFromShip(box_in1.removeDataForShip());
92 box_out2.addDataFromShip(box_in2.removeDataForShip());
95 } else if (port.startsWith("mux")) {
96 box_out1.addDataFromShip(condition ? box_in2.removeDataForShip() : box_in1.removeDataForShip());
98 } else if (port.startsWith("deMux")) {
99 (condition ? box_out2 : box_out1).addDataFromShip(box_in1.removeDataForShip());
104 == FleetSim ==============================================================
106 == FPGA ==============================================================
109 reg [(`DATAWIDTH-1):0] reg_in1;
111 reg [(`DATAWIDTH-1):0] reg_in2;
113 reg [(`PACKET_WIDTH-1):0] reg_in;
122 always @(posedge clk) begin
136 `onread(in1_r, in1_a) have_in1 <= 1; reg_in1 <= in1_d; end
139 `onread(in2_r, in2_a) have_in2 <= 1; reg_in2 <= in2_d; end
142 `onread(in_r, in_a) have_in <= 1; reg_in <= in_d; end
146 `onwrite(out1_r, out1_a) have_out1 <= 0; end
150 `onwrite(out2_r, out2_a) have_out2 <= 0; end
153 if (have_in && !have_out1 && !have_out2) begin
154 zero = reg_in[`DATAWIDTH-1:0] == 0;
155 neg = reg_in[`DATAWIDTH-1];
157 case (reg_in[`PACKET_WIDTH-1:`DATAWIDTH])
178 if (reg_in[`PACKET_WIDTH-1:`DATAWIDTH] <= 5) begin
179 if (have_in1 && have_in2 && !have_out1 && !have_out2) begin
185 out1_d <= fire ? reg_in2 : reg_in1;
186 out2_d <= fire ? reg_in1 : reg_in2;
188 end else if (reg_in[`PACKET_WIDTH-1:`DATAWIDTH] <= 11) begin
189 if (fire && have_in2) begin
194 end else if (!fire && have_in1) begin
223 == Test ==============================================================================
228 == Contributors =========================================================
229 Adam Megacz <megacz@cs.berkeley.edu>