3 == Ports ===========================================================
7 constant REPEAT_C1_V1: 0
8 constant REPEAT_C1_V2: 1
9 constant REPEAT_C2_V1: 2
10 constant REPEAT_C2_V2: 3
11 constant PASS_C1_V1: 4
12 constant PASS_C1_V2: 5
13 constant PASS_C2_V1: 6
14 constant PASS_C2_V2: 7
15 constant DROP_C1_V1: 8
16 constant DROP_C1_V2: 9
17 constant DROP_C2_V1: 10
18 constant DROP_C2_V2: 11
22 == Fleeterpreter ====================================================
23 public void service() { }
25 == FleetSim ==============================================================
27 == FPGA ==============================================================
29 wire [3:0] inOp_d_trunc;
30 assign inOp_d_trunc = inOp_d[3:0];
32 reg [`WORDWIDTH-1:0] temp;
33 initial temp = {`WORDWIDTH{1'b1}};
36 wire op_count; assign op_count = inOp_d_trunc==12;
37 wire op_repeat; assign op_repeat = inOp_d[3:2]==0;
38 wire op_pass; assign op_pass = inOp_d[3:2]==1;
39 wire op_drop; assign op_drop = inOp_d[3:2]==2;
40 wire op_c1; assign op_c1 = (op_repeat || op_pass || op_drop) && !inOp_d[1];
41 wire op_c2; assign op_c2 = (op_repeat || op_pass || op_drop) && inOp_d[1];
42 wire op_v1; assign op_v1 = (op_repeat || op_pass || op_drop) && !inOp_d[0];
43 wire op_v2; assign op_v2 = (op_repeat || op_pass || op_drop) && inOp_d[0];
44 assign out_d_ = op_v1 ? in1_d : op_v2 ? in2_d : temp;
46 // FIXME: REPEAT with a count of zero will not work properly
48 always @(posedge clk) begin
55 if (`inOp_empty) full <= 0;
56 if (`out_draining) begin
57 if (op_count) temp <= temp - in2_d;
58 else temp <= temp - 1;
59 if (op_pass && op_v1) `drain_in1
60 if (op_pass && op_v2) `drain_in2
61 end else if (`inOp_full) begin
63 if (op_count && `in1_full && `in2_full) begin
64 temp <= in1_d[`WORDWIDTH-1:0] - in2_d[`WORDWIDTH-1:0];
67 end else if (op_c1 && `in1_full) begin
68 temp <= in1_d[`WORDWIDTH-1:0]-1;
71 end else if (op_c2 && `in2_full) begin
72 temp <= in2_d[`WORDWIDTH-1:0]-1;
76 end else if (temp[`WORDWIDTH-1]) begin
81 end else if (op_repeat && op_v1) begin
83 end else if (op_repeat && op_v2) begin
86 end else if (`out_empty) begin
89 end else if (op_v1 && `in1_full) begin
90 if (op_drop) begin `drain_in1 temp <= temp-1; end
92 end else if (op_v2 && `in2_full) begin
93 if (op_drop) begin `drain_in2 temp <= temp-1; end
101 == Test =================================================================
103 #ship counter : Counter
154 collect, send to debug.in;
157 == Contributors =========================================================
158 Adam Megacz <megacz@cs.berkeley.edu>