3 == Ports ===========================================================
10 percolate up: DDR2_CAS_B 1
11 percolate up: DDR2_CKE 2
12 percolate up: DDR2_RAS_B 1
13 percolate up: DDR2_WE_B 1
14 percolate up: DDR2_ODT 2
15 percolate up: DDR2_CS0_B 2
16 percolate up: DDR2_CLK_N 2
17 percolate up: DDR2_CLK_P 2
18 percolate up: DDR2_A 14
19 percolate up: DDR2_BA 3
20 percolate inout: DDR2_DQ 64
21 percolate up: DDR2_DM 8
22 percolate inout: DDR2_DQS_N 8
23 percolate inout: DDR2_DQS_P 8
25 percolate inout: I2C_DDR2_SCL 1
26 percolate inout: I2C_DDR2_SDA 1
28 percolate down: CLKBUF_Q1_N 1
29 percolate down: CLKBUF_Q1_P 1
31 == TeX ==============================================================
33 == Fleeterpreter ====================================================
34 public void service() { }
35 == FleetSim ==============================================================
37 == FPGA ==============================================================
39 // Nearly all of this was copied from Greg Gibeling's work; copyright shown below:
41 // Everything here was copied from
42 // GateLib/Firmware/DRAM/Hardware/DDR2SDRAM/Test/FPGA_TOP_ML505_DDR2SDRAMTest.v
44 //==============================================================================
46 //==============================================================================
47 // Copyright (c) 2005-2008, Regents of the University of California
48 // All rights reserved.
50 // Redistribution and use in source and binary forms, with or without modification,
51 // are permitted provided that the following conditions are met:
53 // - Redistributions of source code must retain the above copyright notice,
54 // this list of conditions and the following disclaimer.
55 // - Redistributions in binary form must reproduce the above copyright
56 // notice, this list of conditions and the following disclaimer
57 // in the documentation and/or other materials provided with the
59 // - Neither the name of the University of California, Berkeley nor the
60 // names of its contributors may be used to endorse or promote
61 // products derived from this software without specific prior
62 // written permission.
64 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
65 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
66 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
67 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
68 // ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
69 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
70 // LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
71 // ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
72 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
73 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
74 //==============================================================================
77 ClockFreq = 200000000,
81 DWidth = 128, // 128b SDR internal transfers
82 UWidth = 8, // This will almost ALWAYS be 8
83 BurstLen = 2, // 256b total burst, 2 words DWidth words at SDR, or 4 external words at DDR
89 UCount = DWidth / UWidth,
90 // 128b/8 = 16b per mask means per-byte masking
91 MWidth = (EnableECC || (EnableMask == 0)) ? 0 : UCount,
92 // Unused lower address bits, the -1 is to get a proper log2
93 UAWidth = `log2(UCount-1),
94 TAWidth = CAWidth + RAWidth + BAWidth,
95 // Note that the components are in order according to where in the
96 // address they appear, the -1 is to account for DDR
97 AWidth = TAWidth + UAWidth - 1,
98 ECheck = EnableECC ? 2 : 0,
99 ECorrect = EnableECC ? 1 : 0,
101 EHWidth = `max(`log2(ECheck), 1),
102 ERWidth = `max(`log2(ECheck), 1);
107 reg [AWidth-1:0] CommandAddress;
108 reg [CWidth-1:0] Command;
112 wire [DWidth-1:0] DataIn;
113 wire [MWidth-1:0] DataInMask;
117 wire [DWidth-1:0] DataOut;
118 wire [EHWidth-1:0] DataOutErrorChecked;
119 wire [ERWidth-1:0] DataOutErrorCorrected;
124 wire Clock, ClockD2, ClockP90;
125 wire Clock_DCM, ClockD2_DCM, ClockP90_DCM;
128 reg [`WORDWIDTH:0] out_d;
129 assign out_d_ = out_d;
131 assign DDR2_BA[2] = 1'b0;
132 assign DDR2_CS0_B[1] = 1'b1;
133 assign DDR2_ODT[1] = 1'b0;
134 assign DDR2_CKE[1] = 1'b0;
136 IBUFGDS ClockIBufG(.I(CLKBUF_Q1_P), .IB(CLKBUF_Q1_N), .O(Clock_IBUFG));
141 .DLL_FREQUENCY_MODE("HIGH"),
142 .DUTY_CYCLE_CORRECTION("TRUE"),
143 .FACTORY_JF(16'hF0F0)
151 .CLK90(ClockP90_DCM),
159 // synthesis attribute CLKIN_PERIOD of DCMBase is "5.0"
160 // synthesis attribute CLKDV_DIVIDE of DCMBase is "2.0"
161 // synthesis attribute DLL_FREQUENCY_MODE of DCMBase is "HIGH"
162 // synthesis attribute DUTY_CYCLE_CORRECTION of DCMBase is "TRUE"
163 // synthesis attribute FACTORY_JF of DCMBase is "16'hF0F0"
164 BUFG ClockBufG(.I(Clock_DCM), .O(Clock));
165 BUFG ClockP90BufG(.I(ClockP90_DCM), .O(ClockP90));
166 BUFG ClockD2BufG(.I(ClockD2_DCM), .O(ClockD2));
181 .CommandReset(Reset),
183 .DataOutReset(Reset),
185 .CommandAddress(CommandAddress),
187 .CommandValid(CommandValid),
188 .CommandReady(CommandReady),
190 .DataInMask(DataInMask),
191 .DataInValid(DataInValid),
192 .DataInReady(DataInReady),
194 .DataOutErrorChecked(DataOutErrorChecked),
195 .DataOutErrorCorrected(DataOutErrorCorrected),
196 .DataOutValid(DataOutValid),
197 .DataOutReady(DataOutReady),
200 .DDR2_BA(DDR2_BA[1:0]),
201 .DDR2_RAS_B(DDR2_RAS_B),
202 .DDR2_CAS_B(DDR2_CAS_B),
203 .DDR2_WE_B(DDR2_WE_B),
204 .DDR2_CS0_B(DDR2_CS0_B[0]),
205 .DDR2_ODT(DDR2_ODT[0]),
206 .DDR2_CKE(DDR2_CKE[0]),
208 .DDR2_DQS_P(DDR2_DQS_P),
209 .DDR2_DQS_N(DDR2_DQS_N),
210 .DDR2_CLK_P(DDR2_CLK_P),
211 .DDR2_CLK_N(DDR2_CLK_N));
212 defparam DDR2SDRAM.UWidth = UWidth;
213 defparam DDR2SDRAM.BAWidth = BAWidth;
214 defparam DDR2SDRAM.RAWidth = RAWidth;
215 defparam DDR2SDRAM.CAWidth = CAWidth;
216 defparam DDR2SDRAM.DWidth = DWidth;
217 defparam DDR2SDRAM.BurstLen = BurstLen;
218 defparam DDR2SDRAM.EnableMask = EnableMask;
219 defparam DDR2SDRAM.EnableECC = EnableECC;
220 defparam DDR2SDRAM.Board = Board;
221 defparam DDR2SDRAM.MultiClock = 1;
223 assign DataIn = inDataWrite_d;
224 assign DataInMask = 16'b1111111111111111;
226 always @(posedge clk) begin
238 if (`out_empty) begin
242 if (DataOutReady && DataOutValid && `out_empty) begin
243 out_d <= { 1'b0, DataOut[`WORDWIDTH-1:0] };
247 end else if (DataOutReady && CommandReady && DataInReady && `out_empty) begin
248 if (`inAddrWrite_full && `inDataWrite_full) begin
251 CommandAddress <= inAddrWrite_d;
255 out_d <= { 1'b1, 37'b0 };
258 end else if (`inAddrRead_full) begin
260 CommandAddress <= inAddrRead_d;
270 == Test ==============================================================
300 == Constants ========================================================
302 == Contributors =========================================================
303 Adam Megacz <megacz@cs.berkeley.edu>