3 == Ports ===========================================================
10 percolate up: ddr1_Clk_pin 1
11 percolate up: ddr1_Clk_n_pin 1
12 percolate up: ddr1_Addr_pin 13
13 percolate up: ddr1_BankAddr_pin 2
14 percolate up: ddr1_CAS_n_pin 1
15 percolate up: ddr1_CE_pin 1
16 percolate up: ddr1_CS_n_pin 1
17 percolate up: ddr1_RAS_n_pin 1
18 percolate up: ddr1_WE_n_pin 1
19 percolate up: ddr1_DM_pin 4
20 percolate inout: ddr1_DQS 4
21 percolate inout: ddr1_DQ 32
23 == TeX ==============================================================
25 == Fleeterpreter ====================================================
26 public void service() { }
27 == FleetSim ==============================================================
29 == FPGA ==============================================================
31 wire [31:0] dram_addr;
32 wire [31:0] dram_addr__;
35 wire [63:0] dram_write_data;
36 wire [63:0] dram_read_data;
41 assign dram_addr__ = dram_isread ? inAddrRead_d[31:0] : inAddrWrite_d[31:0];
42 assign dram_addr = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
44 reg [`WORDWIDTH:0] out_d;
45 assign out_d_ = out_d;
49 .clk_freq( 50000000 ),
55 .ddr_a( ddr1_Addr_pin ),
56 .ddr_clk( ddr1_Clk_pin ),
57 .ddr_clk_n( ddr1_Clk_n_pin ),
58 .ddr_ba( ddr1_BankAddr_pin ),
60 .ddr_dm( ddr1_DM_pin ),
62 .ddr_cs_n( ddr1_CS_n_pin ),
63 .ddr_ras_n( ddr1_RAS_n_pin ),
64 .ddr_cas_n( ddr1_CAS_n_pin ),
65 .ddr_we_n( ddr1_WE_n_pin ),
66 .ddr_cke( ddr1_CE_pin ),
72 .fml_wr(!dram_isread && dram_addr_r),
73 .fml_done(dram_addr_a),
74 .fml_rd( dram_isread && dram_addr_r),
76 .fml_din(dram_write_data),
77 .fml_dout(dram_read_data),
81 always @(posedge clk) begin
91 if (dram_addr_r && !dram_addr_a) begin
93 end else if (dram_addr_r && dram_addr_a && !dram_isread) begin
98 out_d <= { 1'b1, 37'b0 };
99 end else if (dram_addr_r && dram_addr_a && dram_isread) begin
103 out_d <= { 1'b0, dram_read_data[36:0] };
104 end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full && !dram_addr_r && !dram_addr_a) begin
107 end else if (`out_empty && `inAddrRead_full && !dram_addr_r && !dram_addr_a) begin
115 == Test ========================================================
120 // ships required in order to run this code
143 send token to memory.inAddrRead;
152 == Constants ========================================================
154 == Contributors =========================================================
155 Adam Megacz <megacz@cs.berkeley.edu>