3 == Ports ===========================================================
10 == TeX ==============================================================
12 == Fleeterpreter ====================================================
13 public void service() { }
14 == FleetSim ==============================================================
16 == FPGA ==============================================================
18 // FIXME: use the other chip (64-bit data bus)
22 reg dram_write_data_push;
23 reg dram_read_data_pop;
24 reg [`DATAWIDTH-1:0] out_d;
26 assign dram_addr_r_ = dram_addr_r;
27 assign dram_isread_ = dram_isread;
28 assign dram_addr_ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
29 assign dram_write_data_push_ = dram_write_data_push;
30 assign dram_read_data_pop_ = dram_read_data_pop;
31 assign dram_write_data_ = inDataWrite_d[31:0];
32 assign out_d_ = out_d;
34 always @(posedge clk) begin
40 dram_read_data_pop <= 0;
44 if (!inAddrRead_r && inAddrRead_a) inAddrRead_a <= 0;
45 if (!inDataWrite_r && inDataWrite_a) inDataWrite_a <= 0;
46 if (!inAddrWrite_r && inAddrWrite_a) inAddrWrite_a <= 0;
47 if ( out_r && out_a) out_r <= 0;
49 if (dram_addr_r && !dram_addr_a) begin
51 end else if (dram_addr_r && dram_addr_a && !dram_isread) begin
55 end else if (dram_addr_r && dram_addr_a && dram_isread) begin
58 out_d <= dram_read_data;
60 end else if (inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !dram_addr_r && !dram_addr_a) begin
63 end else if (inAddrRead_r && !inAddrRead_a && !out_r && !out_a && !dram_addr_r && !dram_addr_a) begin
71 == Test ========================================================
74 == Constants ========================================================
76 == Contributors =========================================================
77 Adam Megacz <megacz@cs.berkeley.edu>