3 == Ports ===========================================================
10 == TeX ==============================================================
12 == Fleeterpreter ====================================================
13 public void service() { }
14 == FleetSim ==============================================================
16 == FPGA ==============================================================
20 reg dram_write_data_push;
21 reg dram_read_data_pop;
22 reg [`DATAWIDTH:0] out_d;
23 wire [31:0] dram_addr__;
25 assign dram_addr_r_ = dram_addr_r;
26 assign dram_isread_ = dram_isread;
27 assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
28 assign dram_addr_ = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
29 assign dram_write_data_push_ = dram_write_data_push;
30 assign dram_read_data_pop_ = dram_read_data_pop;
31 assign dram_write_data_ = inDataWrite_d;
32 // assign dram_write_data_ = inDataWrite_d[(`DATAWIDTH-1):0];
33 assign out_d_ = out_d;
35 always @(posedge clk) begin
41 dram_read_data_pop <= 0;
46 if (!inAddrRead_r_ && inAddrRead_a) inAddrRead_a <= 0;
47 if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0;
48 if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0;
49 if ( out_r && out_a) out_r <= 0;
51 if (dram_addr_r && !dram_addr_a) begin
53 end else if (dram_addr_r && dram_addr_a && !dram_isread) begin
57 out_d <= { 1'b1, 37'b0 };
59 end else if (dram_addr_r && dram_addr_a && dram_isread) begin
62 out_d <= { 1'b0, dram_read_data[36:0] };
64 end else if (!out_r && !out_a && inAddrWrite_r && !inAddrWrite_a && inDataWrite_r && !inDataWrite_a && !dram_addr_r && !dram_addr_a) begin
67 end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a && !dram_addr_r && !dram_addr_a) begin
75 == Test ========================================================
78 == Constants ========================================================
80 == Contributors =========================================================
81 Adam Megacz <megacz@cs.berkeley.edu>