ships/DRAM.ship

   1 ship: DRAM
   2
   3 == Ports ===========================================================
   4 data  in:    inAddrRead
   5 data  in:    inAddrWrite
   6 data  in:    inDataWrite
   7
   8 data  out:   out
   9
  10 percolate up:            ddr1_Clk_pin       1
  11 percolate up:            ddr1_Clk_n_pin     1
  12 percolate up:            ddr1_Addr_pin      13
  13 percolate up:            ddr1_BankAddr_pin  2
  14 percolate up:            ddr1_CAS_n_pin     1
  15 percolate up:            ddr1_CE_pin        1
  16 percolate up:            ddr1_CS_n_pin      1
  17 percolate up:            ddr1_RAS_n_pin     1
  18 percolate up:            ddr1_WE_n_pin      1
  19 percolate up:            ddr1_DM_pin        4
  20 percolate inout:         ddr1_DQS           4
  21 percolate inout:         ddr1_DQ            32
  22
  23 == TeX ==============================================================
  24
  25 == Fleeterpreter ====================================================
  26     public void service() { }
  27 == FleetSim ==============================================================
  28
  29 == FPGA ==============================================================
  30
  31   wire  [31:0]  dram_addr;
  32   wire          dram_addr_r_;
  33   wire          dram_addr_a;
  34   wire          dram_isread_;
  35   wire  [63:0]  dram_write_data_;
  36   wire          dram_write_data_push_;
  37   wire          dram_write_data_full;
  38   wire   [63:0] dram_read_data;
  39   wire          dram_read_data_pop_;
  40   wire          dram_read_data_empty;
  41   wire   [1:0]  dram_read_data_latency;
  42
  43   reg         dram_addr_r;
  44   reg         dram_isread;
  45   reg         dram_write_data_push;
  46   reg         dram_read_data_pop;
  47   reg  [`WORDWIDTH:0]  out_d;
  48   wire [31:0] dram_addr__;
  49
  50   assign dram_addr_r_ = dram_addr_r;
  51   assign dram_isread_ = dram_isread;
  52   assign dram_addr__ = !dram_isread ? inAddrWrite_d[31:0] : inAddrRead_d[31:0];
  53   assign dram_addr_  = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
  54   assign dram_write_data_push_ = dram_write_data_push;
  55   assign dram_read_data_pop_ = dram_read_data_pop;
  56   assign dram_write_data_ = inDataWrite_d;
  57   assign out_d_ = out_d;
  58
  59    ddr_ctrl
  60    #(
  61         .clk_freq( 50000000 ),
  62         .clk_multiply( 12 ),
  63         .clk_divide( 5 ),
  64         .phase_shift( 0 ),
  65         .wait200_init( 26 )
  66    ) ddr_ctrl (
  67           .ddr_a( ddr1_Addr_pin ),
  68           .ddr_clk( ddr1_Clk_pin ),
  69           .ddr_clk_n( ddr1_Clk_n_pin ),
  70           .ddr_ba( ddr1_BankAddr_pin ),
  71           .ddr_dq( ddr1_DQ ),
  72           .ddr_dm( ddr1_DM_pin ),
  73           .ddr_dqs( ddr1_DQS ),
  74           .ddr_cs_n( ddr1_CS_n_pin ),
  75           .ddr_ras_n( ddr1_RAS_n_pin ),
  76           .ddr_cas_n( ddr1_CAS_n_pin ),
  77           .ddr_we_n( ddr1_WE_n_pin ),
  78           .ddr_cke( ddr1_CE_pin ),
  79
  80           .clk(clk),
  81           .reset(!sys_rst_pin),
  82           .rot(3'b100),
  83
  84           .fml_wr(!dram_isread && dram_addr_r),
  85           .fml_done(dram_addr_a),
  86           .fml_rd( dram_isread && dram_addr_r),
  87           .fml_adr(dram_addr),
  88           .fml_din(dram_write_data),
  89           .fml_dout(dram_read_data),
  90           .fml_msk(16'h0)
  91    );
  92
  93   always @(posedge clk) begin
  94
  95     if (!rst) begin
  96       `reset
  97       dram_isread <= 0;
  98       dram_addr_r <= 0;
  99       dram_read_data_pop <= 0;
 100
 101     end else begin
 102       `flush
 103       `cleanup
 104
 105       if (dram_addr_r && !dram_addr_a) begin
 106          // busy
 107       end else if (dram_addr_r &&  dram_addr_a && !dram_isread) begin
 108           dram_addr_r <= 0;
 109           `drain_inDataWrite
 110           `drain_inAddrWrite
 111           `fill_out
 112           out_d <= { 1'b1, 37'b0 };
 113       end else if (dram_addr_r &&  dram_addr_a && dram_isread) begin
 114           dram_addr_r <= 0;
 115           `drain_inAddrRead
 116           `fill_out
 117           out_d <= { 1'b0, dram_read_data[36:0] };
 118       end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full && !dram_addr_r && !dram_addr_a) begin
 119           dram_addr_r <= 1;
 120           dram_isread <= 0;
 121       end else if (`out_empty && `inAddrRead_full && !dram_addr_r && !dram_addr_a) begin
 122           dram_addr_r <= 1;
 123           dram_isread <= 1;
 124       end
 125     end
 126   end
 127
 128
 129 == Test ========================================================
 130 #skip
 131
 132 == Constants ========================================================
 133
 134 == Contributors =========================================================
 135 Adam Megacz <megacz@cs.berkeley.edu>