ships/DRAM.ship

   1 ship: DRAM
   2
   3 == Ports ===========================================================
   4 data  in:    inAddrRead
   5 data  in:    inAddrWrite
   6 data  in:    inDataWrite
   7
   8 data  out:   out
   9
  10 percolate up:            ddr1_Clk_pin       1
  11 percolate up:            ddr1_Clk_n_pin     1
  12 percolate up:            ddr1_Addr_pin      13
  13 percolate up:            ddr1_BankAddr_pin  2
  14 percolate up:            ddr1_CAS_n_pin     1
  15 percolate up:            ddr1_CE_pin        1
  16 percolate up:            ddr1_CS_n_pin      1
  17 percolate up:            ddr1_RAS_n_pin     1
  18 percolate up:            ddr1_WE_n_pin      1
  19 percolate up:            ddr1_DM_pin        4
  20 percolate inout:         ddr1_DQS           4
  21 percolate inout:         ddr1_DQ            32
  22
  23 == TeX ==============================================================
  24
  25 == Fleeterpreter ====================================================
  26     public void service() { }
  27 == FleetSim ==============================================================
  28
  29 == FPGA ==============================================================
  30
  31   wire  [31:0]  dram_addr;
  32   wire  [31:0]  dram_addr__;
  33
  34   wire          dram_addr_a;
  35   wire  [63:0]  dram_write_data;
  36   wire  [63:0]  dram_read_data;
  37
  38   reg           dram_addr_r;
  39   reg           dram_isread;
  40
  41   assign dram_addr__ = dram_isread ? inAddrRead_d[31:0] : inAddrWrite_d[31:0];
  42   assign dram_addr   = { dram_addr__[30:6], 1'b0, dram_addr__[5:0] };
  43
  44   reg  [`WORDWIDTH:0]  out_d;
  45   assign out_d_ = out_d;
  46
  47    ddr_ctrl
  48    #(
  49         .clk_freq( 50000000 ),
  50         .clk_multiply( 12 ),
  51         .clk_divide( 5 ),
  52         .phase_shift( 0 ),
  53         .wait200_init( 26 )
  54    ) ddr_ctrl (
  55           .ddr_a( ddr1_Addr_pin ),
  56           .ddr_clk( ddr1_Clk_pin ),
  57           .ddr_clk_n( ddr1_Clk_n_pin ),
  58           .ddr_ba( ddr1_BankAddr_pin ),
  59           .ddr_dq( ddr1_DQ ),
  60           .ddr_dm( ddr1_DM_pin ),
  61           .ddr_dqs( ddr1_DQS ),
  62           .ddr_cs_n( ddr1_CS_n_pin ),
  63           .ddr_ras_n( ddr1_RAS_n_pin ),
  64           .ddr_cas_n( ddr1_CAS_n_pin ),
  65           .ddr_we_n( ddr1_WE_n_pin ),
  66           .ddr_cke( ddr1_CE_pin ),
  67
  68           .clk(clk),
  69           .reset(!rst),
  70           .rot(3'b100),
  71
  72           .fml_wr(!dram_isread && dram_addr_r),
  73           .fml_done(dram_addr_a),
  74           .fml_rd( dram_isread && dram_addr_r),
  75           .fml_adr(dram_addr),
  76           .fml_din(dram_write_data),
  77           .fml_dout(dram_read_data),
  78           .fml_msk(16'h0)
  79    );
  80
  81   always @(posedge clk) begin
  82
  83     if (!rst) begin
  84       `reset
  85       dram_isread <= 0;
  86       dram_addr_r <= 0;
  87
  88     end else begin
  89       `flush
  90       `cleanup
  91
  92       if (dram_addr_r && !dram_addr_a) begin
  93          // busy
  94       end else if (dram_addr_r &&  dram_addr_a && !dram_isread) begin
  95           dram_addr_r <= 0;
  96           `drain_inDataWrite
  97           `drain_inAddrWrite
  98           `fill_out
  99           out_d <= { 1'b1, 37'b0 };
 100       end else if (dram_addr_r &&  dram_addr_a && dram_isread) begin
 101           dram_addr_r <= 0;
 102           `drain_inAddrRead
 103           `fill_out
 104           out_d <= { 1'b0, dram_read_data[36:0] };
 105       end else if (`out_empty && `inAddrWrite_full && `inDataWrite_full && !dram_addr_r && !dram_addr_a) begin
 106           dram_addr_r <= 1;
 107           dram_isread <= 0;
 108       end else if (`out_empty && `inAddrRead_full && !dram_addr_r && !dram_addr_a) begin
 109           dram_addr_r <= 1;
 110           dram_isread <= 1;
 111       end
 112     end
 113   end
 114
 115
 116 == Test ========================================================
 117 #skip
 118 // expected output
 119 #expect 10
 120
 121 // ships required in order to run this code
 122 #ship debug          : Debug
 123 #ship memory         : DRAM
 124
 125 memory.inAddrWrite:
 126   set word=0;
 127   deliver;
 128   deliver;
 129
 130 memory.inDataWrite:
 131   set word=-1;
 132   deliver;
 133   set word=-1;
 134   deliver;
 135
 136 memory.inAddrRead:
 137   recv token;
 138   set word=0;
 139   deliver;
 140
 141 memory.out:
 142   collect;
 143   collect;
 144   send token to memory.inAddrRead;
 145   collect;
 146   send to debug.in;
 147
 148 debug.in:
 149   set ilc=*;
 150   recv, deliver;
 151
 152
 153 == Constants ========================================================
 154
 155 == Contributors =========================================================
 156 Adam Megacz <megacz@cs.berkeley.edu>