3 == Ports ===========================================================
7 percolate down: uart_in 1
8 percolate up: uart_out 1
9 percolate up: rst_out 1
10 percolate down: rst_in 1
12 == Constants ========================================================
14 == TeX ==============================================================
16 percolate up: uart_rts 1
17 percolate down: uart_cts 1
19 This ship is used for debugging. It has only one port, {\tt in}.
20 Programmers should send debug report values to this port. How such
21 values are reported back to the programmer doing the debugging is left
26 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
27 effectively allow multiple independent ``debug streams''
29 Provide a way to programmatically read back the output of the debug
32 == Fleeterpreter ====================================================
33 public void service() {
34 if (box_in.dataReadyForShip())
35 ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
38 == FleetSim ==============================================================
40 == FPGA ==============================================================
47 reg [`WORDWIDTH-1:0] data_to_host_full_word;
51 assign out_d_ = out_d;
53 wire data_to_host_full;
54 reg [7:0] data_to_host;
55 wire data_to_fleet_empty;
56 wire [7:0] data_to_fleet;
57 reg data_to_host_write_enable;
58 reg data_to_fleet_read_enable;
66 assign rst_out = rst_in || break;
68 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
69 // using a 33Mhz clock,
70 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
71 // using a 100Mhz clock,
72 // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
73 sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
74 sasc_top sasc_top(clk, !rst_in,
83 data_to_fleet_read_enable,
84 data_to_host_write_enable,
90 // break and break are _active high_
91 always @(posedge clk) break_last <= break;
92 assign break_i = break && !break_last;
93 assign break_done = !break && break_last;
96 always @(posedge clk) begin
106 data_to_host_write_enable <= 0;
108 end else if (break_done) begin
109 data_to_host_write_enable <= 1;
112 end else if (send_k) begin
113 data_to_host_write_enable <= 1;
116 end else if (count_out==0 && `in_full) begin
118 data_to_host_full_word <= in_d;
120 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable) begin
121 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
122 data_to_host_full_word <= (data_to_host_full_word >> 6);
123 data_to_host_write_enable <= 1;
124 count_out <= count_out-1;
128 data_to_fleet_read_enable <= 0;
129 if (!data_to_fleet_empty && `out_empty && !data_to_fleet_read_enable) begin
130 out_d <= { out_d[43:0], data_to_fleet[5:0] };
131 data_to_fleet_read_enable <= 1;
132 if (count_in==9) begin
136 count_in <= count_in+1;
143 == UCF =================================================================
145 Net clk_pin LOC=AH15;
146 Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
149 #Net clk_pin LOC=AH17;
150 #Net clk_pin TNM_NET = clk_pin;
151 #TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
157 #Net uart_cts LOC=G6;
158 #Net uart_cts IOSTANDARD = LVCMOS33;
161 #Net uart_rts LOC=F6;
162 #Net uart_rts IOSTANDARD = LVCMOS33;
165 Net uart_in LOC=AG15;
166 #Net uart_in IOSTANDARD = LVCMOS33;
170 Net uart_out LOC=AG20;
171 #Net uart_out IOSTANDARD = LVCMOS33;
175 NET gpio_sw_c LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI
177 NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
178 NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V
179 NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V
180 NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V
181 NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V
183 NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
184 NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
185 NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
186 NET gpio_led_3 LOC="AD26" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
187 NET gpio_led_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
188 NET gpio_led_5 LOC="AD25" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
189 NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
190 NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
196 == Test ================================================================
205 == Contributors =========================================================
206 Adam Megacz <megacz@cs.berkeley.edu>