3 == Ports ===========================================================
7 percolate down: uart_in 1
8 percolate up: uart_out 1
9 percolate up: rst_out 1
10 percolate down: rst_in 1
12 == Constants ========================================================
14 == TeX ==============================================================
16 percolate up: uart_rts 1
17 percolate down: uart_cts 1
19 This ship is used for debugging. It has only one port, {\tt in}.
20 Programmers should send debug report values to this port. How such
21 values are reported back to the programmer doing the debugging is left
26 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
27 effectively allow multiple independent ``debug streams''
29 Provide a way to programmatically read back the output of the debug
32 == Fleeterpreter ====================================================
33 public void service() {
34 if (box_in.dataReadyForShip())
35 ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
38 == FleetSim ==============================================================
40 == FPGA ==============================================================
46 reg [`WORDWIDTH-1:0] data_to_host_full_word;
50 assign out_d_ = out_d;
52 wire data_to_host_full;
53 reg [7:0] data_to_host;
54 wire data_to_fleet_empty;
55 wire [7:0] data_to_fleet;
56 reg data_to_host_write_enable;
57 reg data_to_fleet_read_enable;
58 reg [7:0] force_reset;
66 assign rst_out = rst_in || (force_reset!=0) || break;
68 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
69 // using a 33Mhz clock,
70 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
71 // using a 100Mhz clock,
72 // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
73 sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
74 sasc_top sasc_top(clk, !rst_in,
83 data_to_fleet_read_enable,
84 data_to_host_write_enable,
93 always @(posedge clk) begin
94 if (rst_in || break) begin
105 data_to_host_write_enable <= 0;
106 if (force_reset == 1) begin
108 data_to_host_write_enable <= 1;
113 end else if (force_reset != 0) begin
114 force_reset <= force_reset-1;
115 end else if (count_out==0 && `in_full) begin
117 data_to_host_full_word <= in_d;
119 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
120 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
121 data_to_host_full_word <= (data_to_host_full_word >> 6);
122 data_to_host_write_enable <= 1;
123 count_out <= count_out-1;
124 credits = credits - 1;
128 data_to_fleet_read_enable <= 0;
129 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
131 // Note: if the switch fabric refuses to accept a new item,
132 // we can get deadlocked in a state where sending a reset
133 // code (2'b11) won't have any effect. Probably need to go
134 // back to using the break signal.
137 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
138 data_to_fleet_read_enable <= 1;
139 out_d <= { out_d[43:0], data_to_fleet[5:0] };
140 if (count_in==9) begin
144 count_in <= count_in+1;
147 // command 1: flow control credit
148 end else if (data_to_fleet[7:6] == 2'b01) begin
149 data_to_fleet_read_enable <= 1;
150 credits = credits + data_to_fleet[5:0];
153 // uncommenting this requires changing data_to_host_write_enable
154 // to a blocking assignment, and seems to cause data loss whenever
155 // more than four items are in flight.
157 end else if (data_to_fleet[7:6] == 2'b10 && !data_to_host_full && !data_to_host_write_enable) begin
158 data_to_fleet_read_enable <= 1;
159 data_to_host <= data_to_fleet;
160 data_to_host_write_enable = 1;
163 // command 3: reset (and echo back reset code)
164 end else if (data_to_fleet[7:6] == 2'b11) begin
165 data_to_fleet_read_enable <= 1;
166 data_to_host <= data_to_fleet;
176 == UCF =================================================================
178 Net clk_pin LOC=AH15;
179 Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
182 #Net clk_pin LOC=AH17;
183 #Net clk_pin TNM_NET = clk_pin;
184 #TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
190 #Net uart_cts LOC=G6;
191 #Net uart_cts IOSTANDARD = LVCMOS33;
194 #Net uart_rts LOC=F6;
195 #Net uart_rts IOSTANDARD = LVCMOS33;
198 Net uart_in LOC=AG15;
199 #Net uart_in IOSTANDARD = LVCMOS33;
203 Net uart_out LOC=AG20;
204 #Net uart_out IOSTANDARD = LVCMOS33;
212 == Test ================================================================
221 == Contributors =========================================================
222 Adam Megacz <megacz@cs.berkeley.edu>