3 == Ports ===========================================================
6 percolate up: root_in_r 1
7 percolate down: root_in_a 1
8 percolate up: root_in_d 8
9 percolate down: uart_in 1
10 percolate up: uart_out 1
11 percolate up: uart_rts 1
12 percolate down: uart_cts 1
13 percolate up: rst_out 1
14 percolate down: rst_in 1
16 == Constants ========================================================
18 == TeX ==============================================================
20 This ship is used for debugging. It has only one port, {\tt in}.
21 Programmers should send debug report values to this port. How such
22 values are reported back to the programmer doing the debugging is left
27 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
28 effectively allow multiple independent ``debug streams''
30 Provide a way to programmatically read back the output of the debug
33 == Fleeterpreter ====================================================
34 public void service() {
35 if (box_in.dataReadyForShip())
36 ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
39 == FleetSim ==============================================================
41 == FPGA ==============================================================
45 reg send_k; initial send_k = 0;
47 wire data_to_host_full;
48 wire data_to_host_write_enable;
49 wire [7:0] data_to_host;
51 wire data_to_fleet_empty;
52 wire data_to_fleet_read_enable;
53 wire [7:0] data_to_fleet;
57 reg [7:0] data_to_host_r;
58 assign data_to_host = data_to_host_r;
62 initial ser_rst_r = 0;
63 assign ser_rst = (rst_in & ser_rst_r);
69 assign rst_out = rst_in && !break;
71 sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4);
72 sasc_top sasc_top(clk, ser_rst,
81 data_to_fleet_read_enable,
82 data_to_host_write_enable,
88 // break and break are _active high_
89 always @(posedge clk) break_last <= break;
90 assign break_i = break && !break_last;
91 assign break_done = !break && break_last;
93 reg data_to_host_write_enable_reg;
94 reg data_to_fleet_read_enable_reg;
96 reg [`WORDWIDTH-1:0] root_out_d;
97 reg root_out_r; initial root_out_r = 0;
102 reg [7:0] root_in_d_reg;
103 initial root_in_r_reg = 0;
104 initial root_in_d_reg = 0;
105 initial root_out_a_reg = 0;
106 initial data_to_fleet_read_enable_reg = 0;
107 initial data_to_host_write_enable_reg = 0;
109 assign root_out_a = root_out_a_reg;
110 assign root_in_r = root_in_r_reg;
111 assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
112 assign data_to_host_write_enable = data_to_host_write_enable_reg;
113 assign root_in_d = root_in_d_reg;
116 always @(posedge clk)
120 data_to_host_write_enable_reg <= 0;
122 end else if (break_done) begin
123 data_to_host_write_enable_reg <= 1;
124 data_to_host_r <= 111;
126 end else if (send_k) begin
127 data_to_host_write_enable_reg <= 1;
128 data_to_host_r <= 107;
132 end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
133 data_to_host_write_enable_reg <= 1;
134 data_to_host_r <= root_out_d[7:0];
136 end else if (root_out_a_reg && !root_out_r) begin
137 data_to_host_write_enable_reg <= 0;
140 data_to_host_write_enable_reg <= 0;
145 always @(posedge clk)
151 data_to_fleet_read_enable_reg <= 0;
154 if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
156 root_in_d_reg <= data_to_fleet;
157 data_to_fleet_read_enable_reg <= 1;
159 data_to_fleet_read_enable_reg <= 0;
169 always @(posedge clk) begin
175 if (root_out_r && root_out_a) root_out_r <= 0;
176 if (`in_full && !root_out_r && !root_out_a && count==0) begin
182 if (count!=0 && !root_out_r && !root_out_a) begin
185 root_out_d <= (root_out_d >> 8);
190 == Test ================================================================
199 == Contributors =========================================================
200 Adam Megacz <megacz@cs.berkeley.edu>