3 == Ports ===========================================================
7 percolate down: uart_in 1
8 percolate up: uart_out 1
9 percolate up: rst_out 1
10 percolate down: rst_in 1
12 == Constants ========================================================
14 == TeX ==============================================================
16 percolate up: uart_rts 1
17 percolate down: uart_cts 1
19 This ship is used for debugging. It has only one port, {\tt in}.
20 Programmers should send debug report values to this port. How such
21 values are reported back to the programmer doing the debugging is left
26 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
27 effectively allow multiple independent ``debug streams''
29 Provide a way to programmatically read back the output of the debug
32 == Fleeterpreter ====================================================
33 public void service() {
34 if (box_in.dataReadyForShip())
35 ((Interpreter)getFleet()).debug(box_in.removeDataForShip());
38 == FleetSim ==============================================================
40 == FPGA ==============================================================
46 reg [`WORDWIDTH-1:0] data_to_host_full_word;
50 assign out_d_ = out_d;
52 wire data_to_host_full;
53 reg [7:0] data_to_host;
54 wire data_to_fleet_empty;
55 wire [7:0] data_to_fleet;
56 reg data_to_host_write_enable;
57 reg data_to_fleet_read_enable;
58 reg [7:0] force_reset;
66 assign rst_out = rst_in || (force_reset!=0) /* || break */;
68 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
69 // using a 33Mhz clock,
70 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
71 // using a 100Mhz clock,
72 // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
73 // using a 100Mhz clock, 115200baud
74 // 100Mhz / 115200hz * 4 = 217.013 => 215+2,1 => 215,1
75 // sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
76 sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
77 sasc_top sasc_top(clk, !rst_in,
86 data_to_fleet_read_enable,
87 data_to_host_write_enable,
96 always @(posedge clk) begin
97 if (rst_in /* || break */) begin
108 data_to_host_write_enable <= 0;
109 if (force_reset == 1) begin
111 data_to_host_write_enable <= 1;
116 end else if (force_reset != 0) begin
117 force_reset <= force_reset-1;
118 end else if (count_out==0 && `in_full) begin
120 data_to_host_full_word <= in_d;
122 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
123 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
124 data_to_host_full_word <= (data_to_host_full_word >> 6);
125 data_to_host_write_enable <= 1;
126 count_out <= count_out-1;
127 credits = credits - 1;
131 data_to_fleet_read_enable <= 0;
132 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
134 // Note: if the switch fabric refuses to accept a new item,
135 // we can get deadlocked in a state where sending a reset
136 // code (2'b11) won't have any effect. Probably need to go
137 // back to using the break signal.
140 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
141 data_to_fleet_read_enable <= 1;
142 out_d <= { out_d[43:0], data_to_fleet[5:0] };
143 if (count_in==9) begin
147 count_in <= count_in+1;
150 // command 1: flow control credit
151 end else if (data_to_fleet[7:6] == 2'b01) begin
152 data_to_fleet_read_enable <= 1;
153 credits = credits + data_to_fleet[5:0];
156 // uncommenting this requires changing data_to_host_write_enable
157 // to a blocking assignment, and seems to cause data loss whenever
158 // more than four items are in flight.
160 end else if (data_to_fleet[7:6] == 2'b10 && !data_to_host_full && !data_to_host_write_enable) begin
161 data_to_fleet_read_enable <= 1;
162 data_to_host <= data_to_fleet;
163 data_to_host_write_enable = 1;
166 // command 3: reset (and echo back reset code)
167 end else if (data_to_fleet[7:6] == 2'b11) begin
168 data_to_fleet_read_enable <= 1;
169 data_to_host <= data_to_fleet;
179 == UCF =================================================================
181 Net clk_pin LOC=AH15;
182 Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
185 #Net clk_pin LOC=AH17;
186 #Net clk_pin TNM_NET = clk_pin;
187 #TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
193 #Net uart_cts LOC=G6;
194 #Net uart_cts IOSTANDARD = LVCMOS33;
197 #Net uart_rts LOC=F6;
198 #Net uart_rts IOSTANDARD = LVCMOS33;
201 Net uart_in LOC=AG15;
202 #Net uart_in IOSTANDARD = LVCMOS33;
206 Net uart_out LOC=AG20;
207 #Net uart_out IOSTANDARD = LVCMOS33;
215 == Test ================================================================
224 == Contributors =========================================================
225 Adam Megacz <megacz@cs.berkeley.edu>