3 == Ports ===========================================================
7 percolate down: uart_in 1
8 percolate up: uart_out 1
9 percolate up: rst_out 1
10 percolate down: rst_in 1
11 percolate down: clk_pin 1
12 percolate up: clk_out 1
14 == Constants ========================================================
16 == TeX ==============================================================
18 percolate up: uart_rts 1
19 percolate down: uart_cts 1
21 This ship is used for debugging. It has only one port, {\tt in}.
22 Programmers should send debug report values to this port. How such
23 values are reported back to the programmer doing the debugging is left
28 Provide an {\tt inOp} port and use opcode ports \cite{am25} to
29 effectively allow multiple independent ``debug streams''
31 Provide a way to programmatically read back the output of the debug
34 == Fleeterpreter ====================================================
35 public void service() {
36 if (box_in.dataReadyForShip())
37 ((Interpreter)getFleet()).debug(new BitVector(37).set(box_in.removeDataForShip()));
40 == FleetSim ==============================================================
42 == FPGA ==============================================================
48 reg [`WORDWIDTH-1:0] data_to_host_full_word;
52 assign out_d_ = out_d;
54 wire data_to_host_full;
55 reg [7:0] data_to_host;
56 wire data_to_fleet_empty;
57 wire [7:0] data_to_fleet;
58 reg data_to_host_write_enable;
59 reg data_to_fleet_read_enable;
60 reg [7:0] force_reset;
62 assign clk_out = clk_pin;
70 assign rst_out = rst_in || (force_reset!=0) /* || break */;
72 // fst=3 means clock divider is 3+2=5 for a 50Mhz clock => 10Mhz
73 // using a 33Mhz clock,
74 // 33.333Mhz / 38400hz * 4 = 217.013 => 215+2,1 => 215,1
75 // using a 100Mhz clock,
76 // 100Mhz / 38400hz * 4 = 651.039 => 215+2,3 => 215,3
77 // using a 100Mhz clock, 115200baud
78 // 100Mhz / 115200hz * 4 = 217.013 => 215+2,1 => 215,1
79 // sasc_brg sasc_brg(clk, !rst_in, 215, 3, sio_ce, sio_ce_x4);
80 sasc_brg sasc_brg(clk, !rst_in, 215, 1, sio_ce, sio_ce_x4);
81 sasc_top sasc_top(clk, !rst_in,
90 data_to_fleet_read_enable,
91 data_to_host_write_enable,
100 always @(posedge clk) begin
101 if (rst_in /* || break */) begin
112 data_to_host_write_enable <= 0;
113 if (force_reset == 1) begin
115 data_to_host_write_enable <= 1;
120 end else if (force_reset != 0) begin
121 force_reset <= force_reset-1;
122 end else if (count_out==0 && `in_full) begin
124 data_to_host_full_word <= in_d;
126 end else if (count_out!=0 && !data_to_host_full && !data_to_host_write_enable && credits!=0) begin
127 data_to_host <= { 2'b0, data_to_host_full_word[5:0] };
128 data_to_host_full_word <= (data_to_host_full_word >> 6);
129 data_to_host_write_enable <= 1;
130 count_out <= count_out-1;
131 credits = credits - 1;
135 data_to_fleet_read_enable <= 0;
136 if (!data_to_fleet_empty && !data_to_fleet_read_enable) begin
138 // Note: if the switch fabric refuses to accept a new item,
139 // we can get deadlocked in a state where sending a reset
140 // code (2'b11) won't have any effect. Probably need to go
141 // back to using the break signal.
144 if (data_to_fleet[7:6] == 2'b00 && `out_empty) begin
145 data_to_fleet_read_enable <= 1;
146 out_d <= { out_d[43:0], data_to_fleet[5:0] };
147 if (count_in==9) begin
151 count_in <= count_in+1;
154 // command 1: flow control credit
155 end else if (data_to_fleet[7:6] == 2'b01) begin
156 data_to_fleet_read_enable <= 1;
157 credits = credits + data_to_fleet[5:0];
160 // uncommenting this requires changing data_to_host_write_enable
161 // to a blocking assignment, and seems to cause data loss whenever
162 // more than four items are in flight.
164 end else if (data_to_fleet[7:6] == 2'b10 && !data_to_host_full && !data_to_host_write_enable) begin
165 data_to_fleet_read_enable <= 1;
166 data_to_host <= data_to_fleet;
167 data_to_host_write_enable = 1;
170 // command 3: reset (and echo back reset code)
171 end else if (data_to_fleet[7:6] == 2'b11) begin
172 data_to_fleet_read_enable <= 1;
173 data_to_host <= data_to_fleet;
183 == UCF =================================================================
185 Net clk_pin LOC=AH15;
186 Net clk_pin PERIOD = 10 ns HIGH 50%; # 100Mhz
189 #Net clk_pin LOC=AH17;
190 #Net clk_pin TNM_NET = clk_pin;
191 #TIMESPEC TS_clk_pin = PERIOD clk_pin 30 ns HIGH 50%; # 33Mhz
197 #Net uart_cts LOC=G6;
198 #Net uart_cts IOSTANDARD = LVCMOS33;
201 #Net uart_rts LOC=F6;
202 #Net uart_rts IOSTANDARD = LVCMOS33;
205 Net uart_in LOC=AG15;
206 #Net uart_in IOSTANDARD = LVCMOS33;
210 Net uart_out LOC=AG20;
211 #Net uart_out IOSTANDARD = LVCMOS33;
219 == Test ================================================================
228 == Contributors =========================================================
229 Adam Megacz <megacz@cs.berkeley.edu>