3 == Ports ===========================================================
14 percolate up: dvi_d0 1
15 percolate up: dvi_d1 1
16 percolate up: dvi_d2 1
17 percolate up: dvi_d3 1
18 percolate up: dvi_d4 1
19 percolate up: dvi_d5 1
20 percolate up: dvi_d6 1
21 percolate up: dvi_d7 1
22 percolate up: dvi_d8 1
23 percolate up: dvi_d9 1
24 percolate up: dvi_d10 1
25 percolate up: dvi_d11 1
29 percolate up: dvi_xclk_n 1
30 percolate up: dvi_xclk_p 1
31 percolate up: dvi_de 1
32 percolate up: dvi_reset_b 1
35 percolate up: gpio_led_4 1
36 percolate up: gpio_led_5 1
37 percolate up: gpio_led_6 1
38 percolate up: gpio_led_7 1
40 percolate up: dvi_iic_scl 1
41 percolate inout: dvi_iic_sda 1
43 percolate up: gpio_led_0 1
44 percolate up: gpio_led_1 1
45 percolate up: gpio_led_2 1
46 percolate up: gpio_led_3 1
48 percolate up: sram_adv_ld_b 1
49 percolate up: sram_bw0 1
50 percolate up: sram_bw1 1
51 percolate up: sram_bw2 1
52 percolate up: sram_bw3 1
53 percolate up: sram_clk 1
54 percolate up: sram_cs_b 1
55 percolate up: sram_flash_a0 1
56 percolate up: sram_flash_a1 1
57 percolate up: sram_flash_a2 1
58 percolate up: sram_flash_a3 1
59 percolate up: sram_flash_a4 1
60 percolate up: sram_flash_a5 1
61 percolate up: sram_flash_a6 1
62 percolate up: sram_flash_a7 1
63 percolate up: sram_flash_a8 1
64 percolate up: sram_flash_a9 1
65 percolate up: sram_flash_a10 1
66 percolate up: sram_flash_a11 1
67 percolate up: sram_flash_a12 1
68 percolate up: sram_flash_a13 1
69 percolate up: sram_flash_a14 1
70 percolate up: sram_flash_a15 1
71 percolate up: sram_flash_a16 1
72 percolate up: sram_flash_a17 1
73 percolate up: sram_flash_a18 1
74 percolate up: sram_flash_a19 1
75 percolate up: sram_flash_a20 1
76 percolate up: sram_flash_a21 1
77 percolate up: sram_flash_we_b 1
78 percolate up: sram_mode 1
79 percolate up: sram_oe_b 1
81 percolate inout: sram_dqp0 1
82 percolate inout: sram_dqp1 1
83 percolate inout: sram_dqp2 1
84 percolate inout: sram_dqp3 1
86 percolate inout: sram_flash_d0 1
87 percolate inout: sram_flash_d1 1
88 percolate inout: sram_flash_d2 1
89 percolate inout: sram_flash_d3 1
90 percolate inout: sram_flash_d4 1
91 percolate inout: sram_flash_d5 1
92 percolate inout: sram_flash_d6 1
93 percolate inout: sram_flash_d7 1
94 percolate inout: sram_flash_d8 1
95 percolate inout: sram_flash_d9 1
96 percolate inout: sram_flash_d10 1
97 percolate inout: sram_flash_d11 1
98 percolate inout: sram_flash_d12 1
99 percolate inout: sram_flash_d13 1
100 percolate inout: sram_flash_d14 1
101 percolate inout: sram_flash_d15 1
102 percolate inout: sram_d16 1
103 percolate inout: sram_d17 1
104 percolate inout: sram_d18 1
105 percolate inout: sram_d19 1
106 percolate inout: sram_d20 1
107 percolate inout: sram_d21 1
108 percolate inout: sram_d22 1
109 percolate inout: sram_d23 1
110 percolate inout: sram_d24 1
111 percolate inout: sram_d25 1
112 percolate inout: sram_d26 1
113 percolate inout: sram_d27 1
114 percolate inout: sram_d28 1
115 percolate inout: sram_d29 1
116 percolate inout: sram_d30 1
117 percolate inout: sram_d31 1
119 == FPGA ==============================================================
130 assign dvi_reset_b = 1;
131 assign dvi_de = data_valid_ext;
146 ) my_vga_timing_generator (
154 .DATA_VALID_EXT(data_valid_ext),
159 .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
160 .INIT(1'b0), // Initial value for Q port ('1' or '0')
161 .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
163 .Q(dvi_xclk_p), // 1-bit DDR output
164 .C(pix_clk), // 1-bit clock input
165 .CE(1), // 1-bit clock enable input
166 .D1(1), // 1-bit data input (positive edge)
167 .D2(0), // 1-bit data input (negative edge)
168 .R(0), // 1-bit reset input
169 .S(0) // 1-bit set input
172 .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
173 .INIT(1'b0), // Initial value for Q port ('1' or '0')
174 .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
176 .Q(dvi_xclk_n), // 1-bit DDR output
177 .C(pix_clk), // 1-bit clock input
178 .CE(1), // 1-bit clock enable input
179 .D1(0), // 1-bit data input (positive edge)
180 .D2(1), // 1-bit data input (negative edge)
181 .R(0), // 1-bit reset input
182 .S(0) // 1-bit set input
185 i2c_video_programmer my_i2c_video_programmer_i (
188 .I2C_SDA(dvi_iic_sda),
189 .I2C_SCL(dvi_iic_scl));
192 .CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
193 .CLKFX_DIVIDE(16), // Can be any interger from 1 to 32
194 .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
195 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
196 .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
197 .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
198 .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
199 .DCM_AUTOCALIBRATION("TRUE"), // DCM calibrartion circuitry TRUE/FALSE
200 .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
201 .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
202 .DFS_FREQUENCY_MODE("HIGH"), // LOW or HIGH frequency mode for frequency synthesis
203 .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
204 .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
205 .FACTORY_JF(16'hF0F0), // FACTORY JF Values Suggested to be set to X"F0F0"
206 .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
207 .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
216 ODDR ODDR_dvi_d0 (dvi_d0, pix_clk, 1, dvi_green[4], dvi_blue[0], ~data_valid_ext, 0);
217 ODDR ODDR_dvi_d1 (dvi_d1, pix_clk, 1, dvi_green[5], dvi_blue[1], ~data_valid_ext, 0);
218 ODDR ODDR_dvi_d2 (dvi_d2, pix_clk, 1, dvi_green[6], dvi_blue[2], ~data_valid_ext, 0);
219 ODDR ODDR_dvi_d3 (dvi_d3, pix_clk, 1, dvi_green[7], dvi_blue[3], ~data_valid_ext, 0);
220 ODDR ODDR_dvi_d4 (dvi_d4, pix_clk, 1, dvi_red[0], dvi_blue[4], ~data_valid_ext, 0);
221 ODDR ODDR_dvi_d5 (dvi_d5, pix_clk, 1, dvi_red[1], dvi_blue[5], ~data_valid_ext, 0);
222 ODDR ODDR_dvi_d6 (dvi_d6, pix_clk, 1, dvi_red[2], dvi_blue[6], ~data_valid_ext, 0);
223 ODDR ODDR_dvi_d7 (dvi_d7, pix_clk, 1, dvi_red[3], dvi_blue[7], ~data_valid_ext, 0);
224 ODDR ODDR_dvi_d8 (dvi_d8, pix_clk, 1, dvi_red[4], dvi_green[0], ~data_valid_ext, 0);
225 ODDR ODDR_dvi_d9 (dvi_d9, pix_clk, 1, dvi_red[5], dvi_green[1], ~data_valid_ext, 0);
226 ODDR ODDR_dvi_d10 (dvi_d10, pix_clk, 1, dvi_red[6], dvi_green[2], ~data_valid_ext, 0);
227 ODDR ODDR_dvi_d11 (dvi_d11, pix_clk, 1, dvi_red[7], dvi_green[3], ~data_valid_ext, 0);
232 wire [20:0] vga_pixel_addr_;
233 reg [20:0] vga_pixel_addr;
234 reg [20:0] last_vga_pixel_addr;
238 reg [3:0] wait_until_read;
239 reg [3:0] wait_until_write;
240 reg [3:0] wait_until_video;
242 wire [35:0] data_out;
244 reg [37:0] writeData;
248 assign out_d_ = out_d;
250 assign sram_flash_a0 = use_addr ? addr[0] : 0;
251 assign sram_flash_a1 = use_addr ? addr[1] : vga_pixel_addr[0];
252 assign sram_flash_a2 = use_addr ? addr[2] : vga_pixel_addr[1];
253 assign sram_flash_a3 = use_addr ? addr[3] : vga_pixel_addr[2];
254 assign sram_flash_a4 = use_addr ? addr[4] : vga_pixel_addr[3];
255 assign sram_flash_a5 = use_addr ? addr[5] : vga_pixel_addr[4];
256 assign sram_flash_a6 = use_addr ? addr[6] : vga_pixel_addr[5];
257 assign sram_flash_a7 = use_addr ? addr[7] : vga_pixel_addr[6];
258 assign sram_flash_a8 = use_addr ? addr[8] : vga_pixel_addr[7];
259 assign sram_flash_a9 = use_addr ? addr[9] : vga_pixel_addr[8];
260 assign sram_flash_a10 = use_addr ? addr[10] : vga_pixel_addr[9];
261 assign sram_flash_a11 = use_addr ? addr[11] : vga_pixel_addr[10];
262 assign sram_flash_a12 = use_addr ? addr[12] : vga_pixel_addr[11];
263 assign sram_flash_a13 = use_addr ? addr[13] : vga_pixel_addr[12];
264 assign sram_flash_a14 = use_addr ? addr[14] : vga_pixel_addr[13];
265 assign sram_flash_a15 = use_addr ? addr[15] : vga_pixel_addr[14];
266 assign sram_flash_a16 = use_addr ? addr[16] : vga_pixel_addr[15];
267 assign sram_flash_a17 = use_addr ? addr[17] : vga_pixel_addr[16];
268 assign sram_flash_a18 = use_addr ? addr[18] : vga_pixel_addr[17];
269 assign sram_flash_a19 = use_addr ? addr[19] : vga_pixel_addr[18];
270 assign sram_flash_a20 = use_addr ? addr[20] : vga_pixel_addr[19];
271 assign sram_flash_a21 = use_addr ? addr[21] : vga_pixel_addr[20];
273 assign data_out[0] = sram_flash_d0; assign sram_flash_d0 = oe ? 1'bz : writeData[0];
274 assign data_out[1] = sram_flash_d1; assign sram_flash_d1 = oe ? 1'bz : writeData[1];
275 assign data_out[2] = sram_flash_d2; assign sram_flash_d2 = oe ? 1'bz : writeData[2];
276 assign data_out[3] = sram_flash_d3; assign sram_flash_d3 = oe ? 1'bz : writeData[3];
277 assign data_out[4] = sram_flash_d4; assign sram_flash_d4 = oe ? 1'bz : writeData[4];
278 assign data_out[5] = sram_flash_d5; assign sram_flash_d5 = oe ? 1'bz : writeData[5];
279 assign data_out[6] = sram_flash_d6; assign sram_flash_d6 = oe ? 1'bz : writeData[6];
280 assign data_out[7] = sram_flash_d7; assign sram_flash_d7 = oe ? 1'bz : writeData[7];
281 assign data_out[8] = sram_flash_d8; assign sram_flash_d8 = oe ? 1'bz : writeData[8];
282 assign data_out[9] = sram_flash_d9; assign sram_flash_d9 = oe ? 1'bz : writeData[9];
283 assign data_out[10] = sram_flash_d10; assign sram_flash_d10 = oe ? 1'bz : writeData[10];
284 assign data_out[11] = sram_flash_d11; assign sram_flash_d11 = oe ? 1'bz : writeData[11];
285 assign data_out[12] = sram_flash_d12; assign sram_flash_d12 = oe ? 1'bz : writeData[12];
286 assign data_out[13] = sram_flash_d13; assign sram_flash_d13 = oe ? 1'bz : writeData[13];
287 assign data_out[14] = sram_flash_d14; assign sram_flash_d14 = oe ? 1'bz : writeData[14];
288 assign data_out[15] = sram_flash_d15; assign sram_flash_d15 = oe ? 1'bz : writeData[15];
289 assign data_out[16] = sram_d16; assign sram_d16 = oe ? 1'bz : writeData[16];
290 assign data_out[17] = sram_d17; assign sram_d17 = oe ? 1'bz : writeData[17];
291 assign data_out[18] = sram_d18; assign sram_d18 = oe ? 1'bz : writeData[18];
292 assign data_out[19] = sram_d19; assign sram_d19 = oe ? 1'bz : writeData[19];
293 assign data_out[20] = sram_d20; assign sram_d20 = oe ? 1'bz : writeData[20];
294 assign data_out[21] = sram_d21; assign sram_d21 = oe ? 1'bz : writeData[21];
295 assign data_out[22] = sram_d22; assign sram_d22 = oe ? 1'bz : writeData[22];
296 assign data_out[23] = sram_d23; assign sram_d23 = oe ? 1'bz : writeData[23];
297 assign data_out[24] = sram_d24; assign sram_d24 = oe ? 1'bz : writeData[24];
298 assign data_out[25] = sram_d25; assign sram_d25 = oe ? 1'bz : writeData[25];
299 assign data_out[26] = sram_d26; assign sram_d26 = oe ? 1'bz : writeData[26];
300 assign data_out[27] = sram_d27; assign sram_d27 = oe ? 1'bz : writeData[27];
301 assign data_out[28] = sram_d28; assign sram_d28 = oe ? 1'bz : writeData[28];
302 assign data_out[29] = sram_d29; assign sram_d29 = oe ? 1'bz : writeData[29];
303 assign data_out[30] = sram_d30; assign sram_d30 = oe ? 1'bz : writeData[30];
304 assign data_out[31] = sram_d31; assign sram_d31 = oe ? 1'bz : writeData[31];
305 assign data_out[32] = sram_dqp0; assign sram_dqp0 = oe ? 1'bz : writeData[32];
306 assign data_out[33] = sram_dqp1; assign sram_dqp1 = oe ? 1'bz : writeData[33];
307 assign data_out[34] = sram_dqp2; assign sram_dqp2 = oe ? 1'bz : writeData[34];
308 assign data_out[35] = sram_dqp3; assign sram_dqp3 = oe ? 1'bz : writeData[35];
310 assign sram_mode = 0;
311 assign sram_clk = clk;
312 assign sram_bw0 = ~write_enable;
313 assign sram_bw1 = ~write_enable;
314 assign sram_bw2 = ~write_enable;
315 assign sram_bw3 = ~write_enable;
316 assign sram_flash_we_b = ~write_enable;
317 assign sram_adv_ld_b = 0;
318 assign sram_cs_b = 0;
319 assign sram_oe_b = ~oe;
321 // Framebuffer is 544x478 -- yeah, I know that's completely weird.
325 assign on_screen_ = (x_coord >= 48) && (x_coord < 592);
326 wire [9:0] adjusted_x_coord;
327 assign adjusted_x_coord = x_coord - 48;
329 assign inAddr = inPixelX_d[20:0]
330 + { 7'b0000000, inPixelY_d[8:0], 5'b00000 }
331 + { 3'b000, inPixelY_d[8:0], 9'b0000000000 };
332 assign vga_pixel_addr_ = { 11'b00000000000, adjusted_x_coord }
333 + { 7'b0000000, y_coord[8:0], 5'b00000 }
334 + { 3'b000, y_coord[8:0], 9'b0000000000 };
336 assign dvi_red = on_screen ? { mem_out[17:12], 2'b0 } : 0;
337 assign dvi_green = on_screen ? { mem_out[11:6], 2'b0 } : 0;
338 assign dvi_blue = on_screen ? { mem_out[5:0], 2'b0 } : 0;
340 always @(posedge pix_clk) begin
341 vga_pixel_addr <= vga_pixel_addr_;
342 on_screen <= on_screen_;
346 assign idle = (wait_until_write==0 && wait_until_read==0 && wait_until_video==0);
348 always @(posedge clk) begin
351 wait_until_read <= 0;
352 wait_until_video <= 0;
353 wait_until_write <= 0;
362 if (wait_until_write == 1) begin
363 wait_until_write <= 0;
366 end else if (wait_until_write != 0) begin
367 wait_until_write <= wait_until_write-1;
370 if (wait_until_read == 1) begin
371 wait_until_read <= 0;
372 out_d <= { 1'b0, data_out };
376 end else if (wait_until_read != 0) begin
377 wait_until_read <= wait_until_read-1;
380 if (wait_until_video == 1) begin
381 wait_until_video <= 0;
383 end else if (wait_until_video != 0) begin
384 wait_until_video <= wait_until_video-1;
387 if (`inAddrWrite_full && `inDataWrite_full && idle && `out_empty) begin
389 wait_until_write <= 1;
390 addr <= { inAddrWrite_d, 1'b0 };
391 writeData <= inDataWrite_d;
392 out_d <= { 1'b1, 37'b0 };
398 end else if (`inPixelX_full && `inPixelY_full && `inPixelValue_full && idle) begin
403 wait_until_write <= 1;
404 addr <= { inAddr, 1'b0 };
405 writeData <= inPixelValue_d;
408 end else if (`inAddrRead_full && idle && `out_empty) begin
409 // next cycle (wait_until_read==3) will assert the address for the request
410 // cycle after that (wait_until_read==2) is the gap
411 // cycle after that (wait_until_read==1) will have the valid data being asserted back
412 // unfortunately, I seem to get errors unless I wait for an EXTRA cycle on top of this.
413 // wait_until_read <= 3;
414 wait_until_read <= 4;
415 addr <= { inAddrRead_d, 1'b0 };
418 end else if (last_vga_pixel_addr != vga_pixel_addr && idle && on_screen) begin
419 // wait_until_video can't be more than 3, because (3+1) is the ratio of the pixel clock to the host clock
420 wait_until_video <= 3;
421 addr <= { vga_pixel_addr, 1'b0 };
422 last_vga_pixel_addr <= vga_pixel_addr;
430 == UCF ===============================================================
432 #Net "dvi_0/dvi_xclk_p_unbuffered" PERIOD = 5 ns HIGH 50%;
434 NET dvi_d0 LOC="AB8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
435 NET dvi_d1 LOC="AC8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
436 NET dvi_d2 LOC="AN12" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
437 NET dvi_d3 LOC="AP12" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
438 NET dvi_d4 LOC="AA9" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
439 NET dvi_d5 LOC="AA8" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
440 NET dvi_d6 LOC="AM13" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
441 NET dvi_d7 LOC="AN13" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
442 NET dvi_d8 LOC="AA10" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
443 NET dvi_d9 LOC="AB10" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
444 NET dvi_d10 LOC="AP14" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
445 NET dvi_d11 LOC="AN14" | IOSTANDARD="LVDCI_33"; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
446 NET dvi_de LOC="AE8" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
447 NET dvi_reset_b LOC="AK6" | IOSTANDARD="LVCMOS33"; # Bank 18, Vcco=3.3V, No DCI
448 NET dvi_h LOC="AM12" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
449 NET dvi_v LOC="AM11" | IOSTANDARD="LVDCI_33" | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
450 NET dvi_xclk_n LOC="AL10" | IOSTANDARD="LVCMOS33" | DRIVE=24 | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
451 NET dvi_xclk_p LOC="AL11" | IOSTANDARD="LVCMOS33" | DRIVE=24 | SLEW=FAST; # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
453 NET dvi_gpio1 LOC="N30" | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
454 NET dvi_iic_scl LOC="U27" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
455 NET dvi_iic_sda LOC="T29" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
457 NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
458 NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
459 NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
460 NET gpio_led_3 LOC="AD26" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
461 NET gpio_led_4 LOC="G16"; # Bank 3, Vcco=2.5V, No DCI
462 NET gpio_led_5 LOC="AD25" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
463 NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
464 NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
468 NET sram_adv_ld_b LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
469 NET sram_bw0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
470 NET sram_bw1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
471 NET sram_bw2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
472 NET sram_bw3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
473 NET sram_clk LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI
474 NET sram_clk LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
475 NET sram_cs_b LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
476 NET sram_d16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
477 NET sram_d17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
478 NET sram_d18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
479 NET sram_d19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
480 NET sram_d20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
481 NET sram_d21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
482 NET sram_d22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
483 NET sram_d23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
484 NET sram_d24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
485 NET sram_d25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
486 NET sram_d26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
487 NET sram_d27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
488 NET sram_d28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
489 NET sram_d29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
490 NET sram_d30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
491 NET sram_d31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
492 NET sram_dqp0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
493 NET sram_dqp1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
494 NET sram_dqp2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
495 NET sram_dqp3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
496 NET sram_flash_a0 LOC="K12"; # Bank 1, Vcco=3.3V
497 NET sram_flash_a1 LOC="K13"; # Bank 1, Vcco=3.3V
498 NET sram_flash_a2 LOC="H23"; # Bank 1, Vcco=3.3V
499 NET sram_flash_a3 LOC="G23"; # Bank 1, Vcco=3.3V
500 NET sram_flash_a4 LOC="H12"; # Bank 1, Vcco=3.3V
501 NET sram_flash_a5 LOC="J12"; # Bank 1, Vcco=3.3V
502 NET sram_flash_a6 LOC="K22"; # Bank 1, Vcco=3.3V
503 NET sram_flash_a7 LOC="K23"; # Bank 1, Vcco=3.3V
504 NET sram_flash_a8 LOC="K14"; # Bank 1, Vcco=3.3V
505 NET sram_flash_a9 LOC="L14"; # Bank 1, Vcco=3.3V
506 NET sram_flash_a10 LOC="H22"; # Bank 1, Vcco=3.3V
507 NET sram_flash_a11 LOC="G22"; # Bank 1, Vcco=3.3V
508 NET sram_flash_a12 LOC="J15"; # Bank 1, Vcco=3.3V
509 NET sram_flash_a13 LOC="K16"; # Bank 1, Vcco=3.3V
510 NET sram_flash_a14 LOC="K21"; # Bank 1, Vcco=3.3V
511 NET sram_flash_a15 LOC="J22"; # Bank 1, Vcco=3.3V
512 NET sram_flash_a16 LOC="L16"; # Bank 1, Vcco=3.3V
513 NET sram_flash_a17 LOC="L15"; # Bank 1, Vcco=3.3V
514 NET sram_flash_a18 LOC="L20"; # Bank 1, Vcco=3.3V
515 NET sram_flash_a19 LOC="L21"; # Bank 1, Vcco=3.3V
516 NET sram_flash_a20 LOC="AE23"; # Bank 2, Vcco=3.3V
517 NET sram_flash_a21 LOC="AE22"; # Bank 2, Vcco=3.3V
518 NET sram_flash_d0 LOC="AD19"; # Bank 2, Vcco=3.3V
519 NET sram_flash_d1 LOC="AE19"; # Bank 2, Vcco=3.3V
520 NET sram_flash_d2 LOC="AE17"; # Bank 2, Vcco=3.3V
521 NET sram_flash_d3 LOC="AF16"; # Bank 2, Vcco=3.3V
522 NET sram_flash_d4 LOC="AD20"; # Bank 2, Vcco=3.3V
523 NET sram_flash_d5 LOC="AE21"; # Bank 2, Vcco=3.3V
524 NET sram_flash_d6 LOC="AE16"; # Bank 2, Vcco=3.3V
525 NET sram_flash_d7 LOC="AF15"; # Bank 2, Vcco=3.3V
526 NET sram_flash_d8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI
527 NET sram_flash_d9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI
528 NET sram_flash_d10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI
529 NET sram_flash_d11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI
530 NET sram_flash_d12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI
531 NET sram_flash_d13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI
532 NET sram_flash_d14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI
533 NET sram_flash_d15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI
534 NET sram_flash_we_b LOC="AF20"; # Bank 2, Vcco=3.3V
535 NET sram_mode LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
536 NET sram_oe_b LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
540 == TeX ==============================================================
542 == Fleeterpreter ====================================================
543 private java.awt.Frame frame = null;
544 private java.awt.Panel panel = null;
545 private long[][] bits;
546 public static int SCREEN_WIDTH = 577;
547 public static int SCREEN_HEIGHT = 478;
548 public void service() {
550 if (box_inPixelX.dataReadyForShip() &&
551 box_inPixelY.dataReadyForShip() &&
552 box_inPixelValue.dataReadyForShip()) {
553 x = box_inPixelX.removeDataForShip();
554 y = box_inPixelY.removeDataForShip();
555 d = box_inPixelValue.removeDataForShip();
556 } else if (box_inAddrWrite.dataReadyForShip() &&
557 box_inDataWrite.dataReadyForShip() &&
558 box_out.readyForDataFromShip()) {
559 long addr = box_inAddrWrite.removeDataForShip();
560 x = addr % SCREEN_WIDTH;
561 y = addr / SCREEN_WIDTH;
562 d = box_inDataWrite.removeDataForShip();
563 box_out.addDataFromShip(0,true);
564 } else if (box_inAddrRead.dataReadyForShip() &&
565 box_out.readyForDataFromShip()) {
566 long addr = box_inAddrRead.removeDataForShip();
567 x = addr % SCREEN_WIDTH;
568 y = addr / SCREEN_WIDTH;
569 box_out.addDataFromShip(bits[(int)x][(int)y],false);
575 frame = new java.awt.Frame();
576 bits = new long[SCREEN_WIDTH][SCREEN_HEIGHT];
577 for(int i=0; i<SCREEN_WIDTH; i++) bits[i] = new long[SCREEN_HEIGHT];
578 frame.setSize(SCREEN_WIDTH,SCREEN_HEIGHT);
579 panel = new java.awt.Panel() {
580 public void paint(java.awt.Graphics g_) {
581 java.awt.Graphics2D g2 = (java.awt.Graphics2D)g_;
582 g2.transform(java.awt.geom.AffineTransform.getScaleInstance(((double)panel.getWidth())/SCREEN_WIDTH,
583 ((double)panel.getHeight())/SCREEN_HEIGHT));
584 for(int xx=0; xx<SCREEN_WIDTH; xx++) {
585 for(int yy=0; yy<SCREEN_HEIGHT; yy++) {
586 long d = bits[xx][yy];
587 java.awt.Color c = new java.awt.Color(
588 (int)(((d >> 12) & ~((-1L) << 6)) << 2),
589 (int)(((d >> 6) & ~((-1L) << 6)) << 2),
590 (int)(((d >> 0) & ~((-1L) << 6)) << 2)
593 g2.fillRect((int)xx,(int)yy,1,1);
598 frame.setLayout(new java.awt.BorderLayout());
599 frame.add(panel, java.awt.BorderLayout.CENTER);
600 panel.setBackground(java.awt.Color.black);
603 bits[(int)x][(int)y] = d;
607 == FleetSim ==============================================================
609 == Constants =========================================================
611 == Test ==============================================================
624 send token to debug.in;
628 send token to debug.in;
632 send token to debug.in;
640 == Contributors =========================================================
641 Adam Megacz <megacz@cs.berkeley.edu>