3 == Ports ===========================================================
6 == Constants ========================================================
7 == TeX ==============================================================
8 == Fleeterpreter ====================================================
9 public void service() {
10 //throw new Error("the Execute ship is only for FPGA simulations");
13 == FleetSim ==============================================================
14 == FPGA ==============================================================
17 module execute (clk, in_r, in_a_, in_d,
18 ihorn_r_, ihorn_a, ihorn_d_,
19 dhorn_r_, dhorn_a, dhorn_d_
23 `input(in_r, in_a, in_a_, [(`DATAWIDTH-1):0], in_d)
24 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
25 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
26 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
27 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
32 always @(posedge clk) begin
34 `onwrite(ihorn_r, ihorn_a)
37 end else if (dhorn_full) begin
38 `onwrite(dhorn_r, dhorn_a)
43 case (in_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
51 `packet_data(dhorn_d) = in_d[23:0];
52 `packet_dest(dhorn_d) = in_d[34:24];
64 == Contributors =========================================================
65 Adam Megacz <megacz@cs.berkeley.edu>