3 == Ports ===========================================================
11 == Constants ========================================================
19 == TeX ==============================================================
21 This ship implements a bitwise 3-input {\bf L}ook {\bf U}p {\bf
22 T}able. The least significant eight bits of the {\tt inLut} value
23 form a truth table with three inputs and one output.
25 When values are available at all four inputs they are consumed and a
26 value is produced at {\tt out}. Each bit of {\tt out} is produced by
27 looking up the corresponding bits of {\tt in1}, {\tt in2}, and {\tt
28 in3} in the {\tt inLut} truth table.
30 In particular, the bits {\tt in1}, {\tt in2}, {\tt in3} are
31 concatenated to form a three-bit number, with {\tt in3} as the {\it
32 most significant} bit and {\tt in1} as the {\it least significant
33 bit}. This three-bit number, ranging from 0 to 7 (decimal), is used
34 as a bit index into {\tt inLut}'s value (whose least significant bit
35 is considered ``bit zero'').
38 == Fleeterpreter ====================================================
39 public void service() {
40 if (box_in1.dataReadyForShip() &&
41 box_in2.dataReadyForShip() &&
42 box_in3.dataReadyForShip() &&
43 box_inLut.dataReadyForShip() &&
44 box_out.readyForDataFromShip()) {
45 long a = box_in1.removeDataForShip();
46 long b = box_in2.removeDataForShip();
47 long c = box_in3.removeDataForShip();
48 long lut = box_inLut.removeDataForShip();
50 ret |= ((lut & (1<<0))==0) ? 0 : (~a) & (~b) & (~c);
51 ret |= ((lut & (1<<1))==0) ? 0 : ( a) & (~b) & (~c);
52 ret |= ((lut & (1<<2))==0) ? 0 : (~a) & ( b) & (~c);
53 ret |= ((lut & (1<<3))==0) ? 0 : ( a) & ( b) & (~c);
54 ret |= ((lut & (1<<4))==0) ? 0 : (~a) & (~b) & ( c);
55 ret |= ((lut & (1<<5))==0) ? 0 : ( a) & (~b) & ( c);
56 ret |= ((lut & (1<<6))==0) ? 0 : (~a) & ( b) & ( c);
57 ret |= ((lut & (1<<7))==0) ? 0 : ( a) & ( b) & ( c);
58 box_out.addDataFromShip(ret);
62 == FleetSim ==============================================================
63 == FPGA ==============================================================
66 reg [(`DATAWIDTH-1):0] reg_in1;
68 reg [(`DATAWIDTH-1):0] reg_in2;
70 reg [(`DATAWIDTH-1):0] reg_in3;
72 reg [(`DATAWIDTH-1):0] reg_inLut;
74 wire [(`DATAWIDTH-1):0] out;
77 for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
78 assign out[i] = reg_inLut[{reg_in3[i], reg_in2[i], reg_in1[i]}];
82 always @(posedge clk) begin
91 `onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
94 `onread(in2_r, in2_a) have_in2 = 1; reg_in2 = in2_d; end
97 `onread(in3_r, in3_a) have_in3 = 1; reg_in3 = in3_d; end
99 if (!have_inLut) begin
100 `onread(inLut_r, inLut_a) have_inLut = 1; reg_inLut = inLut_d; end
103 if (have_in1 && have_in2 && have_in3 && have_inLut) begin
105 `onwrite(out_r, out_a)
116 == Test =================================================================
378 lut.in1: literal 85; [*] deliver;
379 lut.in2: literal 51; [*] deliver;
380 lut.in3: literal 15; [*] deliver;
381 lut.out: [*] take, sendto debug.in;
383 // cycle through truth tables using alu as INC
386 load repeat counter with 63;
388 load repeat counter with 63;
390 load repeat counter with 63;
392 load repeat counter with 63;
394 load repeat counter with 3;
402 load loop counter with 2;
403 wait, take, sendto lut.inLut;
407 // acks from debug ship trigger new truth tables
409 [*] take, deliver, notify alu.out;
419 == Contributors =========================================================
420 Adam Megacz <megacz@cs.berkeley.edu>