3 == Ports ===========================================================
11 == Constants ========================================================
19 == TeX ==============================================================
21 This ship implements a bitwise 3-input {\bf L}ook {\bf U}p {\bf
22 T}able. The least significant eight bits of the {\tt inLut} value
23 form a truth table with three inputs and one output.
25 When values are available at all four inputs they are consumed and a
26 value is produced at {\tt out}. Each bit of {\tt out} is produced by
27 looking up the corresponding bits of {\tt in1}, {\tt in2}, and {\tt
28 in3} in the {\tt inLut} truth table.
30 In particular, the bits {\tt in1}, {\tt in2}, {\tt in3} are
31 concatenated to form a three-bit number, with {\tt in3} as the {\it
32 most significant} bit and {\tt in1} as the {\it least significant
33 bit}. This three-bit number, ranging from 0 to 7 (decimal), is used
34 as a bit index into {\tt inLut}'s value (whose least significant bit
35 is considered ``bit zero'').
38 == Fleeterpreter ====================================================
39 public void service() {
40 if (box_in1.dataReadyForShip() &&
41 box_in2.dataReadyForShip() &&
42 box_in3.dataReadyForShip() &&
43 box_inLut.dataReadyForShip() &&
44 box_out.readyForDataFromShip()) {
45 long a = box_in1.removeDataForShip();
46 long b = box_in2.removeDataForShip();
47 long c = box_in3.removeDataForShip();
48 long lut = box_inLut.removeDataForShip();
50 ret |= ((lut & (1<<0))==0) ? 0 : (~a) & (~b) & (~c);
51 ret |= ((lut & (1<<1))==0) ? 0 : ( a) & (~b) & (~c);
52 ret |= ((lut & (1<<2))==0) ? 0 : (~a) & ( b) & (~c);
53 ret |= ((lut & (1<<3))==0) ? 0 : ( a) & ( b) & (~c);
54 ret |= ((lut & (1<<4))==0) ? 0 : (~a) & (~b) & ( c);
55 ret |= ((lut & (1<<5))==0) ? 0 : ( a) & (~b) & ( c);
56 ret |= ((lut & (1<<6))==0) ? 0 : (~a) & ( b) & ( c);
57 ret |= ((lut & (1<<7))==0) ? 0 : ( a) & ( b) & ( c);
58 box_out.addDataFromShip(ret);
62 == FleetSim ==============================================================
63 == FPGA ==============================================================
70 for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
71 assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
75 assign lut = inLut_d[7:0];
77 always @(posedge clk) begin
83 if (out_draining && `out_empty) begin
90 if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
98 == Test =================================================================
360 lut.in1: set word= 85; set ilc=*; deliver;
361 lut.in2: set word= 51; set ilc=*; deliver;
362 lut.in3: set word= 15; set ilc=*; deliver;
363 lut.out: set ilc=*; collect, send to debug.in;
365 // cycle through truth tables using alu as INC
370 set word= Alu.inOp[ADD];
375 set ilc=*; recv, deliver;
379 recv token, collect, send to lut.inLut;
386 set ilc=*; recv, deliver;
388 // acks from debug ship trigger new truth tables
391 recv, deliver, send token to alu.out;
393 recv, deliver, send token to alu.out;
395 recv, deliver, send token to alu.out;
397 recv, deliver, send token to alu.out;
399 recv, deliver, send token to alu.out;
403 == Contributors =========================================================
404 Adam Megacz <megacz@cs.berkeley.edu>