ships/Memory.ship

   1 ship: Memory
   2
   3 == Ports ===========================================================
   4 data  in:    inCBD
   5 data  in:    inAddr.read
   6 data  in:    inAddr.write
   7 data  in:    inAddr.readMany
   8 data  in:    inAddr.writeMany
   9 data  in:    inData
  10 data  in:    inStride
  11 data  in:    inCount
  12
  13 data  out:   out
  14
  15 == Fleeterpreter ====================================================
  16     private long[] mem = new long[0];
  17     public long readMem(int addr) { return mem[addr]; }
  18     public void writeMem(int addr, long val) {
  19         if (addr >= mem.length) {
  20             long[] newmem = new long[addr * 2 + 1];
  21             System.arraycopy(mem, 0, newmem, 0, mem.length);
  22             mem = newmem;
  23         }
  24         mem[addr] = val;
  25     }
  26
  27     public void dispatch(int addr, int size) {
  28         for(int i=addr; i<addr+size; i++) {
  29             Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
  30             ((Interpreter)getFleet()).dispatch(instr, i);
  31         }
  32     }
  33
  34     public void boot(byte[] instructions) {
  35         Interpreter fleet = (Interpreter)getFleet();
  36         // load the iscratch and take note of the 0-address INCBD
  37         long launch = 0;
  38         for(int i=0; i<instructions.length; i+=6) {
  39             long word = 0;
  40             for(int j=0; j<6; j++)
  41                 word = (word << 8) | (instructions[i+j] & 0xff);
  42             writeMem(i/6, word);
  43             if (i==0) launch = word;
  44         }
  45
  46         // dispatch the 0-address INCBD
  47         int base = (int)(launch >> 6);
  48         base = base & ~(0xffffffff << 18);
  49         int size = (int)launch;
  50         size = size & ~(0xffffffff <<  6);
  51         dispatch(base, size);
  52     }
  53
  54     private long stride = 0;
  55     private long count = 0;
  56     private long addr = 0;
  57     private boolean writing = false;
  58
  59     public void service() {
  60         if (box_inCBD.dataReadyForShip()) {
  61             long val = box_inCBD.removeDataForShip();
  62             long addr = val >> 6;
  63             long size = val & 0x3f;
  64             dispatch((int)addr, (int)size);
  65         }
  66         if (count > 0 && writing) {
  67             if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
  68                writeMem((int)addr, box_inData.removeDataForShip());
  69                box_out.addDataFromShip(0);
  70                count--;
  71                addr += stride;
  72             }
  73
  74         } else if (count > 0 && !writing) {
  75             if (box_out.readyForDataFromShip()) {
  76                box_out.addDataFromShip(readMem((int)addr));
  77                count--;
  78                addr += stride;
  79             }
  80
  81         } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
  82             Packet packet = box_inAddr.peekPacketForShip();
  83             if (packet.destination.getDestinationName().equals("read")) {
  84                 box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
  85             } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
  86                 writeMem((int)box_inAddr.removeDataForShip(),
  87                          box_inData.removeDataForShip());
  88                 box_out.addDataFromShip(0);
  89             } else if (packet.destination.getDestinationName().equals("writeMany")
  90                        && box_inStride.dataReadyForShip()
  91                        && box_inCount.dataReadyForShip()) {
  92                 addr = box_inAddr.removeDataForShip();
  93                 stride = box_inStride.removeDataForShip();
  94                 count = box_inCount.removeDataForShip();
  95                 writing = true;
  96             } else if (packet.destination.getDestinationName().equals("readMany")
  97                        && box_inStride.dataReadyForShip()
  98                        && box_inCount.dataReadyForShip()) {
  99                 addr = box_inAddr.removeDataForShip();
 100                 stride = box_inStride.removeDataForShip();
 101                 count = box_inCount.removeDataForShip();
 102                 writing = false;
 103             }
 104         }
 105     }
 106
 107 == FleetSim ==============================================================
 108
 109 == FPGA ==============================================================
 110 `include "macros.v"
 111 `define BRAM_ADDR_WIDTH 14
 112 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
 113 `define BRAM_NAME some_bram
 114
 115 /* bram.inc */
 116 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
 117     input  clk;
 118     input  we;
 119     input  [(`BRAM_ADDR_WIDTH-1):0] a;
 120     input  [(`BRAM_ADDR_WIDTH-1):0] dpra;
 121     input  [(`BRAM_DATA_WIDTH-1):0] di;
 122     output [(`BRAM_DATA_WIDTH-1):0] spo;
 123     output [(`BRAM_DATA_WIDTH-1):0] dpo;
 124     reg    [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 125     reg    [(`BRAM_ADDR_WIDTH-1):0] read_a;
 126     reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
 127     always @(posedge clk) begin
 128         if (we)
 129             ram[a] <= di;
 130         read_a <= a;
 131         read_dpra <= dpra;
 132     end
 133     assign spo = ram[read_a];
 134     assign dpo = ram[read_dpra];
 135 endmodule
 136 /* bram.inc */
 137
 138 module memory (clk,
 139                cbd_r,          cbd_a_,         cbd_d,
 140                in_addr_r,      in_addr_a_,     in_addr_d,
 141                write_data_r,   write_data_a_,  write_data_d,
 142                stride_r,       stride_a_,      stride_d,
 143                count_r,        count_a_,       count_d,
 144                out_r_,         out_a,          out_d_,
 145                preload_r,      preload_a_,     preload_d,
 146                ihorn_r_,       ihorn_a,        ihorn_d_,
 147                dhorn_r_,       dhorn_a,        dhorn_d_
 148               );
 149
 150   input  clk;
 151   `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
 152   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
 153   `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
 154   `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
 155   `output(out_r,         out_r_,        out_a,          [(`DATAWIDTH-1):0],         out_d_)
 156   //`defreg(out_d_,                                     [(`DATAWIDTH-1):0],         out_d)
 157
 158   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
 159   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
 160   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
 161   `defreg(ihorn_d_,                                     [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
 162   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
 163   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
 164
 165   reg ihorn_full;
 166   initial ihorn_full = 0;
 167   reg dhorn_full;
 168   initial dhorn_full = 0;
 169   reg command_valid;
 170   initial command_valid = 0;
 171
 172   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
 173   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
 174   initial preload_size = 0;
 175
 176   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
 177   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
 178   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
 179   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
 180   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
 181   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
 182   reg [(`INSTRUCTION_WIDTH-1):0]  command;
 183   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 184   reg                             send_done;
 185   reg                             send_read;
 186
 187   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
 188   reg [(`DATAWIDTH-1):0]                                     data;
 189
 190   reg                             write_flag;
 191   reg [(`BRAM_ADDR_WIDTH-1):0]    in_addr;
 192   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
 193
 194   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
 195
 196   reg command_valid_read;
 197   initial command_valid_read = 0;
 198
 199   reg launched;
 200   initial launched = 0;
 201
 202   some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
 203   assign out_d_ = ramread;
 204
 205   always @(posedge clk) begin
 206
 207     write_flag <= 0;
 208
 209     if (!in_addr_r && in_addr_a) in_addr_a = 0;
 210     if (!write_data_r && write_data_a) write_data_a = 0;
 211
 212     if (command_valid_read) begin
 213       command_valid_read  <= 0;
 214       command_valid       <= 1;
 215
 216     end else  if (send_done) begin
 217       `onwrite(out_r, out_a)
 218         send_done <= 0;
 219       end
 220
 221     end else  if (send_read) begin
 222       `onwrite(out_r, out_a)
 223         send_read <= 0;
 224       end
 225
 226     end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
 227       in_addr_a                        = 1;
 228       send_read                       <= 1;
 229       current_instruction_read_from   <= in_addr_d[(`DATAWIDTH-1):0];
 230
 231     end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
 232       in_addr_a          = 1;
 233       write_data_a       = 1;
 234       send_done         <= 1;
 235       write_flag        <= 1;
 236       in_addr           <= in_addr_d[(`DATAWIDTH-1):0];
 237       write_data        <= write_data_d;
 238
 239     end else if (ihorn_full && launched) begin
 240       `onwrite(ihorn_r, ihorn_a)
 241         ihorn_full <= 0;
 242       end
 243
 244     end else if (dhorn_full) begin
 245       `onwrite(dhorn_r, dhorn_a)
 246         dhorn_full <= 0;
 247       end
 248
 249     end else if (command_valid) begin
 250       command_valid <= 0;
 251       command = ramread;
 252       case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
 253         0: begin
 254             ihorn_full  <= 1;
 255             ihorn_d     <= command;
 256            end
 257         1: begin
 258             dhorn_full  <= 1;
 259             temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
 260             temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
 261             data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
 262             data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
 263             `packet_data(dhorn_d) <= temp;
 264             `packet_dest(dhorn_d) <=
 265                   command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
 266            end
 267         2: begin
 268             dhorn_full            <= 1;
 269             `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
 270             `packet_dest(dhorn_d) <= command[34:24];
 271            end
 272         3: begin
 273             dhorn_full            <= 1;
 274             `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
 275             `packet_dest(dhorn_d) <= command[34:24];
 276            end
 277       endcase
 278
 279     end else if (cbd_pos < cbd_size) begin
 280       current_instruction_read_from <= cbd_base+cbd_pos;
 281       command_valid_read            <= 1;
 282       cbd_pos                       <= cbd_pos + 1;
 283
 284     end else begin
 285       `onread(cbd_r, cbd_a)
 286         cbd_pos       <= 0;
 287         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 288         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 289
 290       end else begin
 291         `onread(preload_r, preload_a)
 292           if (preload_size == 0) begin
 293             preload_size     <= preload_d;
 294           end else if (!launched) begin
 295             write_flag <= 1;
 296             write_data <= preload_d;
 297             in_addr <= preload_pos;
 298             if (preload_pos == 0) begin
 299               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 300               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 301             end
 302             if ((preload_pos+1) == preload_size) begin
 303               cbd_pos  <= 0;
 304               cbd_base <= temp_base;
 305               cbd_size <= temp_size;
 306               launched <= 1;
 307             end
 308             preload_pos      <= preload_pos + 1;
 309           end
 310         end
 311       end
 312     end
 313   end
 314 endmodule
 315
 316
 317
 318
 319
 320 == Test ==============================================================
 321 // expected output
 322 #expect 12
 323 #expect 13
 324 #expect 14
 325
 326 // ships required in order to run this code
 327 #ship debug          : Debug
 328 #ship memory         : Memory
 329
 330 // instructions not in any codebag are part of the "root codebag"
 331 // which is dispatched when the code is loaded
 332
 333 BOB:              sendto memory.inCBD;
 334 memory.inCBD:     [*] take, deliver;
 335 debug.in:         [*] take, deliver;
 336
 337
 338 // This codebag illustrates how to do a loop.  Notice that this
 339 // is actually an uncontrolled data emitter -- it could clog the
 340 //  switch fabric!
 341
 342 BOB: {
 343   12:           sendto debug.in;
 344   13:           sendto debug.in;
 345   14:           sendto debug.in;
 346 }
 347
 348
 349 == Constants ========================================================
 350 == TeX ==============================================================
 351 \begin{verbatim}
 352 TODO: count/stride
 353 TODO: multiple interfaces to a single memory
 354 \end{verbatim}
 355
 356 == Contributors =========================================================
 357 Adam Megacz <megacz@cs.berkeley.edu>