3 == Ports ===========================================================
7 data in: inAddr.readMany
8 data in: inAddr.writeMany
15 == Fleeterpreter ====================================================
16 private long[] mem = new long[0];
17 public long readMem(int addr) { return mem[addr]; }
18 public void writeMem(int addr, long val) {
19 if (addr >= mem.length) {
20 long[] newmem = new long[addr * 2 + 1];
21 System.arraycopy(mem, 0, newmem, 0, mem.length);
27 public void dispatch(int addr, int size) {
28 for(int i=addr; i<addr+size; i++) {
29 Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
30 ((Interpreter)getFleet()).dispatch(instr, i);
34 public void boot(byte[] instructions) {
35 Interpreter fleet = (Interpreter)getFleet();
36 // load the iscratch and take note of the 0-address INCBD
38 for(int i=0; i<instructions.length; i+=6) {
40 for(int j=0; j<6; j++)
41 word = (word << 8) | (instructions[i+j] & 0xff);
43 if (i==0) launch = word;
46 // dispatch the 0-address INCBD
47 int base = (int)(launch >> 6);
48 base = base & ~(0xffffffff << 18);
49 int size = (int)launch;
50 size = size & ~(0xffffffff << 6);
54 public void service() {
55 if (box_inCBD.dataReadyForShip()) {
56 long val = box_inCBD.removeDataForShip();
58 long size = val & 0x3f;
59 dispatch((int)addr, (int)size);
61 if (box_inAddr.dataReadyForShip() && box_out.readyForItemFromShip()) {
62 Packet packet = box_inAddr.peekPacketForShip();
63 if (packet.destination.getDestinationName().equals("read")) {
64 box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
65 } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
66 writeMem((int)box_inAddr.removeDataForShip(),
67 box_inData.removeDataForShip());
68 box_out.addDataFromShip(0);
73 == FleetSim ==============================================================
75 == FPGA ==============================================================
77 `define BRAM_ADDR_WIDTH 14
78 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
79 `define BRAM_NAME some_bram
84 in_addr_r, in_addr_a_, in_addr_d,
85 write_data_r, write_data_a_, write_data_d,
86 stride_r, stride_a_, stride_d,
87 count_r, count_a_, count_d,
88 out_r_, out_a, out_d_,
89 preload_r, preload_a_, preload_d,
90 ihorn_r_, ihorn_a, ihorn_d_,
91 dhorn_r_, dhorn_a, dhorn_d_
95 `input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
96 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
97 `input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
98 `input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
99 `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
100 //`defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
102 `input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
103 `input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
104 `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
105 `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
106 `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
107 `defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
110 initial ihorn_full = 0;
112 initial dhorn_full = 0;
114 initial command_valid = 0;
116 reg [(`BRAM_ADDR_WIDTH-1):0] preload_pos;
117 reg [(`BRAM_ADDR_WIDTH-1):0] preload_size;
118 initial preload_size = 0;
120 reg [(`BRAM_ADDR_WIDTH-1):0] current_instruction_read_from;
121 reg [(`BRAM_ADDR_WIDTH-1):0] temp_base;
122 reg [(`CODEBAG_SIZE_BITS-1):0] temp_size;
123 reg [(`BRAM_ADDR_WIDTH-1):0] cbd_base;
124 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_size;
125 reg [(`CODEBAG_SIZE_BITS-1):0] cbd_pos;
126 reg [(`INSTRUCTION_WIDTH-1):0] command;
127 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
131 reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
132 reg [(`DATAWIDTH-1):0] data;
135 reg [(`BRAM_ADDR_WIDTH-1):0] in_addr;
136 reg [(`BRAM_DATA_WIDTH-1):0] write_data;
138 wire [(`BRAM_DATA_WIDTH-1):0] ramread;
140 reg command_valid_read;
141 initial command_valid_read = 0;
144 initial launched = 0;
146 some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
147 assign out_d_ = ramread;
149 always @(posedge clk) begin
153 if (!in_addr_r && in_addr_a) in_addr_a = 0;
154 if (!write_data_r && write_data_a) write_data_a = 0;
156 if (command_valid_read) begin
157 command_valid_read <= 0;
160 end else if (send_done) begin
161 `onwrite(out_r, out_a)
165 end else if (send_read) begin
166 `onwrite(out_r, out_a)
170 end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
173 current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
175 end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
180 in_addr <= in_addr_d[(`DATAWIDTH-1):0];
181 write_data <= write_data_d;
183 end else if (ihorn_full && launched) begin
184 `onwrite(ihorn_r, ihorn_a)
188 end else if (dhorn_full) begin
189 `onwrite(dhorn_r, dhorn_a)
193 end else if (command_valid) begin
196 case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
203 temp = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
204 temp = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
205 data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
206 data[(`CODEBAG_SIZE_BITS-1):0] = command[(`CODEBAG_SIZE_BITS-1):0];
207 `packet_data(dhorn_d) <= temp;
208 `packet_dest(dhorn_d) <=
209 command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
213 `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
214 `packet_dest(dhorn_d) <= command[34:24];
218 `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
219 `packet_dest(dhorn_d) <= command[34:24];
223 end else if (cbd_pos < cbd_size) begin
224 current_instruction_read_from <= cbd_base+cbd_pos;
225 command_valid_read <= 1;
226 cbd_pos <= cbd_pos + 1;
229 `onread(cbd_r, cbd_a)
231 cbd_size <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
232 cbd_base <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
235 `onread(preload_r, preload_a)
236 if (preload_size == 0) begin
237 preload_size <= preload_d;
238 end else if (!launched) begin
240 write_data <= preload_d;
241 in_addr <= preload_pos;
242 if (preload_pos == 0) begin
243 temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
244 temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
246 if ((preload_pos+1) == preload_size) begin
248 cbd_base <= temp_base;
249 cbd_size <= temp_size;
252 preload_pos <= preload_pos + 1;
266 == Constants ========================================================
267 == TeX ==============================================================
269 == Contributors =========================================================
270 Adam Megacz <megacz@cs.berkeley.edu>