ships/Memory.ship

   1 ship: Memory
   2
   3 == Ports ===========================================================
   4 data  in:    inCBD
   5 data  in:    inAddrRead
   6 data  in:    inAddrWrite
   7 data  in:    inDataWrite
   8 data  in:    inStride
   9 data  in:    inCount
  10
  11 data  out:   out
  12
  13 == Fleeterpreter ====================================================
  14     private long[] mem = new long[0];
  15     public long readMem(int addr) { return mem[addr]; }
  16     public void writeMem(int addr, long val) {
  17         if (addr >= mem.length) {
  18             long[] newmem = new long[addr * 2 + 1];
  19             System.arraycopy(mem, 0, newmem, 0, mem.length);
  20             mem = newmem;
  21         }
  22         mem[addr] = val;
  23     }
  24
  25     public void dispatch(int addr, int size) {
  26         for(int i=addr; i<addr+size; i++) {
  27             Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
  28             ((Interpreter)getFleet()).dispatch(instr, i);
  29         }
  30     }
  31
  32     public void boot(byte[] instructions) {
  33         Interpreter fleet = (Interpreter)getFleet();
  34         // load the iscratch and take note of the 0-address INCBD
  35         long launch = 0;
  36         for(int i=0; i<instructions.length; i+=6) {
  37             long word = 0;
  38             for(int j=0; j<6; j++)
  39                 word = (word << 8) | (instructions[i+j] & 0xff);
  40             writeMem(i/6, word);
  41             if (i==0) launch = word;
  42         }
  43
  44         // dispatch the 0-address INCBD
  45         int base = (int)(launch >> 6);
  46         base = base & ~(0xffffffff << 18);
  47         int size = (int)launch;
  48         size = size & ~(0xffffffff <<  6);
  49         dispatch(base, size);
  50     }
  51
  52     private long stride = 0;
  53     private long count = 0;
  54     private long addr = 0;
  55     private boolean writing = false;
  56
  57     public void service() {
  58         if (box_inCBD.dataReadyForShip()) {
  59             long val = box_inCBD.removeDataForShip();
  60             long addr = val >> 6;
  61             long size = val & 0x3f;
  62             dispatch((int)addr, (int)size);
  63         }
  64         if (count > 0 && writing) {
  65             if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
  66                writeMem((int)addr, box_inDataWrite.removeDataForShip());
  67                box_out.addDataFromShip(0);
  68                count--;
  69                addr += stride;
  70             }
  71
  72         } else if (count > 0 && !writing) {
  73             if (box_out.readyForDataFromShip()) {
  74                box_out.addDataFromShip(readMem((int)addr));
  75                count--;
  76                addr += stride;
  77             }
  78
  79         } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
  80             Packet packet = box_inAddrRead.peekPacketForShip();
  81             if (packet.destination.getDestinationName().equals("read")) {
  82                 box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()));
  83             } else if (packet.destination.getDestinationName().equals("write") && box_inDataWrite.dataReadyForShip()) {
  84                 writeMem((int)box_inAddrRead.removeDataForShip(),
  85                          box_inDataWrite.removeDataForShip());
  86                 box_out.addDataFromShip(0);
  87             } else if (packet.destination.getDestinationName().equals("writeMany")
  88                        && box_inStride.dataReadyForShip()
  89                        && box_inCount.dataReadyForShip()) {
  90                 addr = box_inAddrRead.removeDataForShip();
  91                 stride = box_inStride.removeDataForShip();
  92                 count = box_inCount.removeDataForShip();
  93                 writing = true;
  94             } else if (packet.destination.getDestinationName().equals("readMany")
  95                        && box_inStride.dataReadyForShip()
  96                        && box_inCount.dataReadyForShip()) {
  97                 addr = box_inAddrRead.removeDataForShip();
  98                 stride = box_inStride.removeDataForShip();
  99                 count = box_inCount.removeDataForShip();
 100                 writing = false;
 101             }
 102         }
 103     }
 104
 105 == FleetSim ==============================================================
 106
 107 == FPGA ==============================================================
 108 `include "macros.v"
 109 `define BRAM_ADDR_WIDTH 14
 110 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
 111 `define BRAM_NAME some_bram
 112
 113 /* bram.inc */
 114 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
 115     input  clk;
 116     input  we;
 117     input  [(`BRAM_ADDR_WIDTH-1):0] a;
 118     input  [(`BRAM_ADDR_WIDTH-1):0] dpra;
 119     input  [(`BRAM_DATA_WIDTH-1):0] di;
 120     output [(`BRAM_DATA_WIDTH-1):0] spo;
 121     output [(`BRAM_DATA_WIDTH-1):0] dpo;
 122     reg    [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 123     reg    [(`BRAM_ADDR_WIDTH-1):0] read_a;
 124     reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
 125     always @(posedge clk) begin
 126         if (we)
 127             ram[a] <= di;
 128         read_a <= a;
 129         read_dpra <= dpra;
 130     end
 131     assign spo = ram[read_a];
 132     assign dpo = ram[read_dpra];
 133 endmodule
 134 /* bram.inc */
 135
 136 module memory (clk,
 137                cbd_r,          cbd_a_,         cbd_d,
 138                in_addr_r,      in_addr_a_,     in_addr_d,
 139                write_addr_r,   write_addr_a_,  write_addr_d,
 140                write_data_r,   write_data_a_,  write_data_d,
 141                stride_r,       stride_a_,      stride_d,
 142                count_r,        count_a_,       count_d,
 143                out_r_,         out_a,          out_d_,
 144                preload_r,      preload_a_,     preload_d,
 145                ihorn_r_,       ihorn_a,        ihorn_d_,
 146                dhorn_r_,       dhorn_a,        dhorn_d_
 147               );
 148
 149   input  clk;
 150   `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
 151   `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(2+`DATAWIDTH-1):0],       write_addr_d)
 152   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
 153   `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
 154   `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
 155   `output(out_r,         out_r_,        out_a,          [(`DATAWIDTH-1):0],         out_d_)
 156   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
 157   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
 158   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`PACKET_WIDTH-1):0], ihorn_d_)
 159   `defreg(ihorn_d_,                                     [(`PACKET_WIDTH-1):0], ihorn_d)
 160   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
 161   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
 162
 163   reg ihorn_full;
 164   initial ihorn_full = 0;
 165   reg dhorn_full;
 166   initial dhorn_full = 0;
 167   reg command_valid;
 168   initial command_valid = 0;
 169
 170   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
 171   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
 172   initial preload_size = 0;
 173
 174   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
 175   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
 176   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
 177   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
 178   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
 179   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
 180   reg [(`INSTRUCTION_WIDTH-1):0]  command;
 181   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 182   reg                             send_done;
 183   reg                             send_read;
 184
 185   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
 186   reg [(`DATAWIDTH-1):0]                                     data;
 187
 188   reg                             write_flag;
 189   reg [(`BRAM_ADDR_WIDTH-1):0]    in_addr;
 190   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
 191
 192   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
 193
 194   reg command_valid_read;
 195   initial command_valid_read = 0;
 196
 197   reg launched;
 198   initial launched = 0;
 199
 200   some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
 201   assign out_d_ = ramread;
 202
 203   always @(posedge clk) begin
 204
 205     write_flag <= 0;
 206
 207     if (!in_addr_r && in_addr_a) in_addr_a = 0;
 208     if (!write_data_r && write_data_a) write_data_a = 0;
 209     if (!write_addr_r && write_addr_a) write_addr_a = 0;
 210
 211     if (command_valid_read) begin
 212       command_valid_read  <= 0;
 213       command_valid       <= 1;
 214
 215     end else  if (send_done) begin
 216       `onwrite(out_r, out_a)
 217         send_done <= 0;
 218       end
 219
 220     end else  if (send_read) begin
 221       `onwrite(out_r, out_a)
 222         send_read <= 0;
 223       end
 224
 225     end else if (in_addr_r) begin
 226       in_addr_a                        = 1;
 227       send_read                       <= 1;
 228       current_instruction_read_from   <= in_addr_d[(`DATAWIDTH-1):0];
 229
 230     end else if (write_addr_r && write_data_r) begin
 231       write_addr_a       = 1;
 232       write_data_a       = 1;
 233       send_done         <= 1;
 234       write_flag        <= 1;
 235       in_addr           <= write_addr_d[(`DATAWIDTH-1):0];
 236       write_data        <= write_data_d;
 237
 238     end else if (ihorn_full && launched) begin
 239       `onwrite(ihorn_r, ihorn_a)
 240         ihorn_full <= 0;
 241       end
 242
 243     end else if (dhorn_full) begin
 244       `onwrite(dhorn_r, dhorn_a)
 245         dhorn_full <= 0;
 246       end
 247
 248     end else if (command_valid) begin
 249       command_valid <= 0;
 250       command = ramread;
 251       ihorn_full  <= 1;
 252         `packet_data(ihorn_d) <= `instruction_data(command);
 253         `packet_dest(ihorn_d) <= `instruction_dest(command);
 254       end
 255
 256     end else if (cbd_pos < cbd_size) begin
 257       current_instruction_read_from <= cbd_base+cbd_pos;
 258       command_valid_read            <= 1;
 259       cbd_pos                       <= cbd_pos + 1;
 260
 261     end else begin
 262       `onread(cbd_r, cbd_a)
 263         cbd_pos       <= 0;
 264         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 265         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 266
 267       end else begin
 268         `onread(preload_r, preload_a)
 269           if (preload_size == 0) begin
 270             preload_size     <= preload_d;
 271           end else if (!launched) begin
 272             write_flag <= 1;
 273             write_data <= preload_d;
 274             in_addr <= preload_pos;
 275             if (preload_pos == 0) begin
 276               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 277               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 278             end
 279             if ((preload_pos+1) == preload_size) begin
 280               cbd_pos  <= 0;
 281               cbd_base <= temp_base;
 282               cbd_size <= temp_size;
 283               launched <= 1;
 284             end
 285             preload_pos      <= preload_pos + 1;
 286           end
 287         end
 288       end
 289     end
 290   end
 291 endmodule
 292
 293
 294
 295
 296
 297 == Test ==============================================================
 298 // expected output
 299 #expect 12
 300 #expect 13
 301 #expect 14
 302
 303 // ships required in order to run this code
 304 #ship debug          : Debug
 305 #ship memory         : Memory
 306
 307 // instructions not in any codebag are part of the "root codebag"
 308 // which is dispatched when the code is loaded
 309
 310 memory.inCBD:
 311   literal BOB;
 312   deliver;
 313
 314 BOB: {
 315   debug.in:
 316     literal 12; deliver;
 317     literal 13; deliver;
 318     literal 14; deliver;
 319 }
 320
 321
 322 == Constants ========================================================
 323 == TeX ==============================================================
 324 \begin{verbatim}
 325 TODO: count/stride
 326 TODO: multiple interfaces to a single memory
 327 \end{verbatim}
 328
 329 == Contributors =========================================================
 330 Adam Megacz <megacz@cs.berkeley.edu>