ships/Memory.ship

   1 ship: Memory
   2
   3 == Ports ===========================================================
   4 data  in:    inCBD
   5 data  in:    inAddrRead
   6 data  in:    inAddrWrite
   7 data  in:    inDataWrite
   8 data  in:    inStride
   9 data  in:    inCount
  10
  11 data  out:   out
  12
  13 == Fleeterpreter ====================================================
  14     private long[] mem = new long[0];
  15     public long readMem(int addr) { return mem[addr]; }
  16     public void writeMem(int addr, long val) {
  17         if (addr >= mem.length) {
  18             long[] newmem = new long[addr * 2 + 1];
  19             System.arraycopy(mem, 0, newmem, 0, mem.length);
  20             mem = newmem;
  21         }
  22         mem[addr] = val;
  23     }
  24
  25     public void dispatch(int addr, int size) {
  26         for(int i=addr; i<addr+size; i++) {
  27             Instruction instr = ((Interpreter)getFleet()).readInstruction(readMem(i));
  28             ((Interpreter)getFleet()).dispatch(instr, i);
  29         }
  30     }
  31
  32     public void boot(byte[] instructions) {
  33         Interpreter fleet = (Interpreter)getFleet();
  34         // load the iscratch and take note of the 0-address INCBD
  35         long launch = 0;
  36         for(int i=0; i<instructions.length; i+=6) {
  37             long word = 0;
  38             for(int j=0; j<6; j++)
  39                 word = (word << 8) | (instructions[i+j] & 0xff);
  40             writeMem(i/6, word);
  41             if (i==0) launch = word;
  42         }
  43
  44         // dispatch the 0-address INCBD
  45         int base = (int)(launch >> 6);
  46         base = base & ~(0xffffffff << 18);
  47         int size = (int)launch;
  48         size = size & ~(0xffffffff <<  6);
  49         dispatch(base, size);
  50     }
  51
  52     private long stride = 0;
  53     private long count = 0;
  54     private long addr = 0;
  55     private boolean writing = false;
  56
  57     public void service() {
  58         if (box_inCBD.dataReadyForShip()) {
  59             long val = box_inCBD.removeDataForShip();
  60             long addr = val >> 6;
  61             long size = val & 0x3f;
  62             dispatch((int)addr, (int)size);
  63         }
  64         if (count > 0 && writing) {
  65             if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
  66                writeMem((int)addr, box_inDataWrite.removeDataForShip());
  67                box_out.addDataFromShip(0);
  68                count--;
  69                addr += stride;
  70             }
  71
  72         } else if (count > 0 && !writing) {
  73             if (box_out.readyForDataFromShip()) {
  74                box_out.addDataFromShip(readMem((int)addr));
  75                count--;
  76                addr += stride;
  77             }
  78
  79         } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
  80             Packet packet = box_inAddrRead.peekPacketForShip();
  81             if (packet.destination.getDestinationName().equals("read")) {
  82                 box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()));
  83             } else if (packet.destination.getDestinationName().equals("write") && box_inDataWrite.dataReadyForShip()) {
  84                 writeMem((int)box_inAddrRead.removeDataForShip(),
  85                          box_inDataWrite.removeDataForShip());
  86                 box_out.addDataFromShip(0);
  87             } else if (packet.destination.getDestinationName().equals("writeMany")
  88                        && box_inStride.dataReadyForShip()
  89                        && box_inCount.dataReadyForShip()) {
  90                 addr = box_inAddrRead.removeDataForShip();
  91                 stride = box_inStride.removeDataForShip();
  92                 count = box_inCount.removeDataForShip();
  93                 writing = true;
  94             } else if (packet.destination.getDestinationName().equals("readMany")
  95                        && box_inStride.dataReadyForShip()
  96                        && box_inCount.dataReadyForShip()) {
  97                 addr = box_inAddrRead.removeDataForShip();
  98                 stride = box_inStride.removeDataForShip();
  99                 count = box_inCount.removeDataForShip();
 100                 writing = false;
 101             }
 102         }
 103     }
 104
 105 == FleetSim ==============================================================
 106
 107 == FPGA ==============================================================
 108 `include "macros.v"
 109 `define BRAM_ADDR_WIDTH 14
 110 `define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
 111 `define BRAM_NAME some_bram
 112
 113 /* bram.inc */
 114 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
 115     input  clk;
 116     input  we;
 117     input  [(`BRAM_ADDR_WIDTH-1):0] a;
 118     input  [(`BRAM_ADDR_WIDTH-1):0] dpra;
 119     input  [(`BRAM_DATA_WIDTH-1):0] di;
 120     output [(`BRAM_DATA_WIDTH-1):0] spo;
 121     output [(`BRAM_DATA_WIDTH-1):0] dpo;
 122     reg    [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 123     reg    [(`BRAM_ADDR_WIDTH-1):0] read_a;
 124     reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
 125     always @(posedge clk) begin
 126         if (we)
 127             ram[a] <= di;
 128         read_a <= a;
 129         read_dpra <= dpra;
 130     end
 131     assign spo = ram[read_a];
 132     assign dpo = ram[read_dpra];
 133 endmodule
 134 /* bram.inc */
 135
 136 module memory (clk,
 137                cbd_r,          cbd_a_,         cbd_d,
 138                in_addr_r,      in_addr_a_,     in_addr_d,
 139                write_addr_r,   write_addr_a_,  write_addr_d,
 140                write_data_r,   write_data_a_,  write_data_d,
 141                stride_r,       stride_a_,      stride_d,
 142                count_r,        count_a_,       count_d,
 143                out_r_,         out_a,          out_d_,
 144                preload_r,      preload_a_,     preload_d,
 145                ihorn_r_,       ihorn_a,        ihorn_d_,
 146                dhorn_r_,       dhorn_a,        dhorn_d_
 147               );
 148
 149   input  clk;
 150   `input(in_addr_r,      in_addr_a,     in_addr_a_,     [(2+`DATAWIDTH-1):0],       in_addr_d)
 151   `input(write_addr_r,   write_addr_a,  write_addr_a_,  [(2+`DATAWIDTH-1):0],       write_addr_d)
 152   `input(write_data_r,   write_data_a,  write_data_a_,  [(`DATAWIDTH-1):0],         write_data_d)
 153   `input(stride_r,       stride_a,      stride_a_,      [(`DATAWIDTH-1):0],         stride_d)
 154   `input(count_r,        count_a,       count_a_,       [(`DATAWIDTH-1):0],         count_d)
 155   `output(out_r,         out_r_,        out_a,          [(`DATAWIDTH-1):0],         out_d_)
 156   //`defreg(out_d_,                                     [(`DATAWIDTH-1):0],         out_d)
 157
 158   `input(preload_r,      preload_a,     preload_a_,     [(`DATAWIDTH-1):0],         preload_d)
 159   `input(cbd_r,          cbd_a,         cbd_a_,         [(`DATAWIDTH-1):0],         cbd_d)
 160   `output(ihorn_r,       ihorn_r_,      ihorn_a,        [(`PACKET_WIDTH-1):0], ihorn_d_)
 161   `defreg(ihorn_d_,                                     [(`PACKET_WIDTH-1):0], ihorn_d)
 162   `output(dhorn_r,       dhorn_r_,      dhorn_a,        [(`PACKET_WIDTH-1):0],      dhorn_d_)
 163   `defreg(dhorn_d_,                                     [(`PACKET_WIDTH-1):0],      dhorn_d)
 164
 165   reg ihorn_full;
 166   initial ihorn_full = 0;
 167   reg dhorn_full;
 168   initial dhorn_full = 0;
 169   reg command_valid;
 170   initial command_valid = 0;
 171
 172   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_pos;
 173   reg [(`BRAM_ADDR_WIDTH-1):0]    preload_size;
 174   initial preload_size = 0;
 175
 176   reg [(`BRAM_ADDR_WIDTH-1):0]    current_instruction_read_from;
 177   reg [(`BRAM_ADDR_WIDTH-1):0]    temp_base;
 178   reg [(`CODEBAG_SIZE_BITS-1):0]  temp_size;
 179   reg [(`BRAM_ADDR_WIDTH-1):0]    cbd_base;
 180   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_size;
 181   reg [(`CODEBAG_SIZE_BITS-1):0]  cbd_pos;
 182   reg [(`INSTRUCTION_WIDTH-1):0]  command;
 183   reg [(`BRAM_DATA_WIDTH-1):0]    ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
 184   reg                             send_done;
 185   reg                             send_read;
 186
 187   reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
 188   reg [(`DATAWIDTH-1):0]                                     data;
 189
 190   reg                             write_flag;
 191   reg [(`BRAM_ADDR_WIDTH-1):0]    in_addr;
 192   reg [(`BRAM_DATA_WIDTH-1):0]    write_data;
 193
 194   wire [(`BRAM_DATA_WIDTH-1):0]   ramread;
 195
 196   reg command_valid_read;
 197   initial command_valid_read = 0;
 198
 199   reg launched;
 200   initial launched = 0;
 201
 202   some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
 203   assign out_d_ = ramread;
 204
 205   always @(posedge clk) begin
 206
 207     write_flag <= 0;
 208
 209     if (!in_addr_r && in_addr_a) in_addr_a = 0;
 210     if (!write_data_r && write_data_a) write_data_a = 0;
 211     if (!write_addr_r && write_addr_a) write_addr_a = 0;
 212
 213     if (command_valid_read) begin
 214       command_valid_read  <= 0;
 215       command_valid       <= 1;
 216
 217     end else  if (send_done) begin
 218       `onwrite(out_r, out_a)
 219         send_done <= 0;
 220       end
 221
 222     end else  if (send_read) begin
 223       `onwrite(out_r, out_a)
 224         send_read <= 0;
 225       end
 226
 227     end else if (in_addr_r) begin
 228       in_addr_a                        = 1;
 229       send_read                       <= 1;
 230       current_instruction_read_from   <= in_addr_d[(`DATAWIDTH-1):0];
 231
 232     end else if (write_addr_r && write_data_r) begin
 233       write_addr_a       = 1;
 234       write_data_a       = 1;
 235       send_done         <= 1;
 236       write_flag        <= 1;
 237       in_addr           <= write_addr_d[(`DATAWIDTH-1):0];
 238       write_data        <= write_data_d;
 239
 240     end else if (ihorn_full && launched) begin
 241       `onwrite(ihorn_r, ihorn_a)
 242         ihorn_full <= 0;
 243       end
 244
 245     end else if (dhorn_full) begin
 246       `onwrite(dhorn_r, dhorn_a)
 247         dhorn_full <= 0;
 248       end
 249
 250     end else if (command_valid) begin
 251       command_valid <= 0;
 252       command = ramread;
 253       case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
 254         0: begin
 255             ihorn_full  <= 1;
 256             `packet_data(ihorn_d) <= `instruction_data(command);
 257             `packet_dest(ihorn_d) <= `instruction_dest(command);
 258            end
 259         1: begin
 260             dhorn_full  <= 1;
 261             temp    = command[(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0];
 262             temp    = temp + ( { current_instruction_read_from, {(`CODEBAG_SIZE_BITS){1'b0}} });
 263             data[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)] = temp;
 264             data[(`CODEBAG_SIZE_BITS-1):0]            = command[(`CODEBAG_SIZE_BITS-1):0];
 265             `packet_data(dhorn_d) <= temp;
 266             `packet_dest(dhorn_d) <=
 267                   command[(`INSTRUCTION_WIDTH-3):(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)+1)];
 268            end
 269         2: begin
 270             dhorn_full            <= 1;
 271             `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] };
 272             `packet_dest(dhorn_d) <= command[34:24];
 273            end
 274         3: begin
 275             dhorn_full            <= 1;
 276             `packet_data(dhorn_d) <= { {(`DATAWIDTH-24){command[23]}}, command[23:0] } + current_instruction_read_from;
 277             `packet_dest(dhorn_d) <= command[34:24];
 278            end
 279       endcase
 280
 281     end else if (cbd_pos < cbd_size) begin
 282       current_instruction_read_from <= cbd_base+cbd_pos;
 283       command_valid_read            <= 1;
 284       cbd_pos                       <= cbd_pos + 1;
 285
 286     end else begin
 287       `onread(cbd_r, cbd_a)
 288         cbd_pos       <= 0;
 289         cbd_size      <= cbd_d[(`CODEBAG_SIZE_BITS-1):0];
 290         cbd_base      <= cbd_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)];
 291
 292       end else begin
 293         `onread(preload_r, preload_a)
 294           if (preload_size == 0) begin
 295             preload_size     <= preload_d;
 296           end else if (!launched) begin
 297             write_flag <= 1;
 298             write_data <= preload_d;
 299             in_addr <= preload_pos;
 300             if (preload_pos == 0) begin
 301               temp_base = preload_d[(`INSTRUCTION_WIDTH-(3+`DESTINATION_ADDRESS_BITS)):(`CODEBAG_SIZE_BITS)];
 302               temp_size = preload_d[(`CODEBAG_SIZE_BITS-1):0];
 303             end
 304             if ((preload_pos+1) == preload_size) begin
 305               cbd_pos  <= 0;
 306               cbd_base <= temp_base;
 307               cbd_size <= temp_size;
 308               launched <= 1;
 309             end
 310             preload_pos      <= preload_pos + 1;
 311           end
 312         end
 313       end
 314     end
 315   end
 316 endmodule
 317
 318
 319
 320
 321
 322 == Test ==============================================================
 323 // expected output
 324 #expect 12
 325 #expect 13
 326 #expect 14
 327
 328 // ships required in order to run this code
 329 #ship debug          : Debug
 330 #ship memory         : Memory
 331
 332 // instructions not in any codebag are part of the "root codebag"
 333 // which is dispatched when the code is loaded
 334
 335 BOB:              sendto memory.inCBD;
 336 memory.inCBD:     [*] take, deliver;
 337 debug.in:         [*] take, deliver;
 338
 339
 340 // This codebag illustrates how to do a loop.  Notice that this
 341 // is actually an uncontrolled data emitter -- it could clog the
 342 //  switch fabric!
 343
 344 BOB: {
 345   12:           sendto debug.in;
 346   13:           sendto debug.in;
 347   14:           sendto debug.in;
 348 }
 349
 350
 351 == Constants ========================================================
 352 == TeX ==============================================================
 353 \begin{verbatim}
 354 TODO: count/stride
 355 TODO: multiple interfaces to a single memory
 356 \end{verbatim}
 357
 358 == Contributors =========================================================
 359 Adam Megacz <megacz@cs.berkeley.edu>