3 == Ports ===========================================================
6 == Constants ========================================================
8 == TeX ==============================================================
9 == Fleeterpreter ====================================================
10 public void service() {
13 == FleetSim ==============================================================
15 == FPGA ==============================================================
17 reg [`WORDWIDTH-1:0] out_d;
18 assign out_d_ = out_d;
20 always @(posedge clk) begin
27 out_d <= {out_d, out_d[17] ~^ out_d[10]};
33 == Test =================================================================
36 == Contributors =========================================================
37 Adam Megacz <megacz@cs.berkeley.edu>