3 == Ports ===========================================================
7 == Constants ========================================================
9 == TeX ==============================================================
10 A stack ship with capacity for at least 16 elements.
12 Push operations are executed as soon as an inbound datum is delivered
13 to the {\tt push} port. Completion of a push can be confirmed by
14 sending a token from the {\tt push} port after {\tt deliver}ing.
16 Pop operations are executed no earlier than the time at which the {\tt
17 pop} port attempts to {\tt take} data from the ship.
19 When the stack becomes full, it will simply not process any new {\tt
20 push} operations. When the stack becomes empty, it will simply not
21 process any new {\tt pop} operations. Phrased another way, if a {\tt
22 pop} is issued to an empty stack, that operation will wait for a {\tt
23 push} to occur; at some point after that, the {\tt pop} will proceed
24 to pop the pushed value. There is no ``underflow'' or ``overflow.''
28 There is some difficulty here when it comes to arbitration -- does the
29 execution of the instruction after the {\tt deliver} to the {\tt push}
30 port indicate that the value has been safely pushed? This is much
31 tricker than it seems.
33 Perhaps there should be a single port, {\tt operation}, to which
34 either a {\sc PUSH} or {\sc POP} command is sent. This would simplify
35 the arbitration issues.
37 == Fleeterpreter ====================================================
38 private ArrayList<Long> stack = new ArrayList<Long>();
39 public void service() {
40 if (box_push.dataReadyForShip() && stack.size()<32) {
41 stack.add(box_push.removeDataForShip());
43 if (box_pop.readyForDataFromShip() && stack.size() > 0) {
44 box_pop.addDataFromShip(stack.get(stack.size()-1));
45 stack.remove(stack.size()-1);
49 == FleetSim ==============================================================
50 == FPGA ==============================================================
51 /* FIXME: inefficient */
52 reg [(`DATAWIDTH-1):0] mem [4:0];
57 always @(posedge clk or negedge rst) begin
62 `onwrite(pop_r, pop_a)
64 pop_d <= mem[depth-2];
70 if (!skip && depth < 32) begin
71 `onread(push_r, push_a)
81 == Test ====================================================
91 debug.in: [*] take, deliver;
93 stack.pop: wait; [*] take, sendto debug.in;
106 == Contributors =========================================================
107 Adam Megacz <megacz@cs.berkeley.edu>