src/edu/berkeley/fleet/fpga/Fpga.java

   1 package edu.berkeley.fleet.fpga;
   2 import edu.berkeley.fleet.fpga.*;
   3 import edu.berkeley.fleet.api.*;
   4 import edu.berkeley.fleet.two.*;
   5 import edu.berkeley.fleet.*;
   6 import java.lang.reflect.*;
   7 import edu.berkeley.sbp.chr.*;
   8 import edu.berkeley.sbp.misc.*;
   9 import edu.berkeley.sbp.meta.*;
  10 import edu.berkeley.sbp.util.*;
  11 import java.util.*;
  12 import java.io.*;
  13 import edu.berkeley.fleet.two.*;
  14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
  15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
  16
  17
  18 /*
  19 => get rid of getInputPort(String) and instead use members
  20 => clean up fabricelement methods
  21 => get rid of addcrap
  22 => automatic width-setting on ports
  23 => nuke DATAWIDTH?
  24   => serdes and fastclock/slowclock?
  25 */
  26
  27 public class Fpga extends FleetTwoFleet {
  28
  29     public  Module top;
  30     public  FabricElement top_horn;
  31     Ship debugShip;
  32
  33     public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
  34     public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
  35
  36     public Ship getShip(String type, int ordinal) {
  37         for(Ship s : this)
  38             if (s.getType().equals(type))
  39                 if (ordinal-- < 0)
  40                     return s;
  41         return null;
  42     }
  43
  44     public static void main(String[] s) throws Exception {
  45         new Fpga(new Module("root")).top.dump(s[0]);
  46     }
  47
  48     public FleetProcess run(Instruction[] instructions) {
  49         try {
  50             return new Client(this, "none", instructions);
  51         } catch (Exception e) { throw new RuntimeException(e); }
  52     }
  53
  54     // Setup //////////////////////////////////////////////////////////////////////////////
  55
  56     public Ship createShip(String type, String name) throws IOException {
  57         ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
  58         FpgaShip ship = new FpgaShip(this, sd);
  59         ships.put(name, ship);
  60         return ship;
  61     }
  62
  63     public Fpga() throws Exception { this(new Module("root")); }
  64     public Fpga(Module top) throws Exception {
  65         this.top = top;
  66         debugShip = createShip("Debug",     "debug");
  67
  68         int LANES = 6;
  69
  70         createShip("Memory",    "memory1");
  71
  72         if (LANES>1)
  73             createShip("Memory",    "memory2");
  74
  75         for(int i=0; i<LANES; i++) {
  76             createShip("Fifo",      "fifo"+i);
  77             createShip("Fifo",      "fifo"+i+"x");
  78             createShip("Alu2",      "alu"+i);
  79             createShip("Alu2",      "alu"+i+"x");
  80         }
  81         createShip("Rotator",   "rotator");
  82         createShip("Lut3",      "lut");
  83         createShip("Rotator",   "rotator_");
  84         createShip("Lut3",      "lut_");
  85
  86         if (LANES<=1)
  87             createShip("Fifo",      "fifo_extra");
  88
  89         createShip("DRAM",    "dram");
  90         createShip("Video",   "video");
  91
  92         //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
  93         Module.SourcePort  debug_out   = null;
  94         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
  95             if (ship.getType().toLowerCase().equals("debug"))
  96                 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
  97         }
  98
  99         // for FifoShip
 100         new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
 101
 102         Module.SourcePort  in          = top.createInputPort("in", 8);
 103         Module.SinkPort    out         = top.createOutputPort("out", 8, "");
 104         Module.Latch       temp_in     = top.new Latch("temp", WIDTH_PACKET) { public String doReset() { return name+"=0;"; } };
 105         Module.Latch       count       = top.new Latch("count", 8);
 106         Module.Latch       count_out   = top.new Latch("count_out", 8);
 107
 108         ArrayList inbox_sources = new ArrayList<FabricElement>();
 109         ArrayList inbox_dests   = new ArrayList<FabricElement>();
 110         ArrayList outbox_sources = new ArrayList<FabricElement>();
 111         ArrayList outbox_dests   = new ArrayList<FabricElement>();
 112         ArrayList instruction_dests   = new ArrayList<FabricElement>();
 113         int numdocks = 0;
 114         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
 115             if (ship.getType().toLowerCase().equals("debug"))
 116                 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
 117             for(Dock port : ship) {
 118                 if (port.isInputDock()) {
 119                     inbox_sources.add(((FpgaDock)port));
 120                     instruction_dests.add(port.getInstructionDestination());
 121                     inbox_dests.add(port.getDataDestination());
 122                 } else {
 123                     outbox_sources.add(((FpgaDock)port));
 124                     instruction_dests.add(port.getInstructionDestination());
 125                     outbox_dests.add(port.getDataDestination());
 126                 }
 127                 numdocks++;
 128             }
 129         }
 130         //System.err.println("dock count = " + numdocks);
 131         ArrayList dests   = new ArrayList<FabricElement>();
 132         ArrayList sources = new ArrayList<FabricElement>();
 133         sources.addAll(inbox_sources);
 134         sources.addAll(outbox_sources);
 135         dests.addAll(inbox_dests);
 136         dests.addAll(instruction_dests);
 137         dests.addAll(outbox_dests);
 138         top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
 139         FabricElement   source  = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
 140         FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(top, null, source.getOutputPort());
 141         ((FunnelModule.FunnelInstance)source).out = top_funnel;
 142         //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
 143         top_funnel.addOutput(top_horn, top_horn.getInputPort());
 144
 145         //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
 146         Module.SinkPort debug_in = top_funnel.getInputPort("in1");
 147
 148         top.new Event(new Object[] { in, debug_in },
 149                       new Object[] { new SimpleAction(temp_in.getVerilogName()+" = ("+temp_in.getVerilogName()+" << 8) | in;"),
 150                                      new SimpleAction("if (count >= 5) begin"+
 151                                                           " count <= 0; "+
 152                                                           " `packet_token("+debug_in.getVerilogName()+") <= 0;"+
 153                                                           " `packet_data("+debug_in.getVerilogName()+") <= "+temp_in.getVerilogName()+";"+
 154                                                           " `packet_dest("+debug_in.getVerilogName()+") <= `instruction_dest("+temp_in.getVerilogName()+");"+
 155                                                           " "+debug_in.getVerilogName()+"_r <= 1; "+
 156                                                           "end else count <= count+1; "),
 157                                      in
 158                   });
 159         top.new Event(new Object[] { out, debug_out },
 160                       new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
 161                                      new SimpleAction("if (count_out >= 5) begin "+
 162                                                           "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
 163                                                           " else count_out <= count_out+1; "),
 164                                      out });
 165
 166     }
 167
 168     public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
 169     public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
 170         switch(end-start) {
 171             case 0: return null;
 172             case 1: return ports[start];
 173             default: {
 174                 FabricElement leftPort  = mkNode(ports, is_horn,  start,         (end+start)/2);
 175                 FabricElement rightPort = mkNode(ports, is_horn,  (end+start)/2, end);
 176                 return is_horn
 177                     ? new HornModule.HornInstance(top,     leftPort, rightPort)
 178                     : new FunnelModule.FunnelInstance(top, leftPort, rightPort);
 179             }
 180         }
 181     }
 182
 183     public Module getVerilogModule() { return top; }
 184
 185
 186     // Expand //////////////////////////////////////////////////////////////////////////////
 187
 188     public void expand(ShipDescription sd) {
 189         try {
 190             if (sd.getSection("fpga")==null) return;
 191             String filename = sd.getName().toLowerCase();
 192             File outf = new File("build/fpga/"+filename+".v");
 193             new File(outf.getParent()).mkdirs();
 194             System.err.println("writing to " + outf);
 195             FileOutputStream out = new FileOutputStream(outf);
 196             PrintWriter pw = new PrintWriter(out);
 197
 198             boolean auto = !"debug".equals(filename);
 199
 200             pw.println("`include \"bitfields.v\"");
 201             pw.println("`define defreg(signame,width,regname) reg width regname; wire width signame;  assign signame = regname; initial regname = 0;");
 202             pw.println("`define input(r, a, a_, w, d)  input r;  output a_; reg a; assign a_=a; input  w d; initial a=0;");
 203             pw.println("`define output(r, r_, a, w, d) output r_; input a;  reg r; assign r_=r; output w d; initial r=0;");
 204             pw.println("`define onread(req, ack)        if (!req && ack) ack <= 0;    else if (req && !ack)  begin ack <=1;");
 205             pw.println("`define onwrite(req, ack)       if (!req && !ack) req <= 1; else if (req && ack)   begin req <= 0;");
 206             pw.println();
 207
 208             if (auto) {
 209                 pw.print("`define reset ");
 210                 for(DockDescription bb : sd) {
 211                     String bb_name = bb.getName();
 212                     if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; ");
 213                     else              pw.print(bb_name+"_r <= 0; ");
 214                 }
 215                 pw.println();
 216
 217                 pw.println("module " + filename + "( clk, rst ");
 218                 for(DockDescription bb : sd) {
 219                     String bb_name = bb.getName();
 220                     pw.print("        ");
 221                     if (bb.isInputDock()) {
 222                         pw.print(", " + bb_name+"_r");
 223                         pw.print(", " + bb_name+"_a_");
 224                         pw.print(", " + bb_name+"_d");
 225                     } else {
 226                         pw.print(", " + bb_name+"_r_");
 227                         pw.print(", " + bb_name+"_a");
 228                         pw.print(", " + bb_name+"_d_");
 229                     }
 230                     pw.println();
 231                 }
 232                 if (filename.equals("dram")) {
 233                     pw.println("    , dram_addr_");
 234                     pw.println("    , dram_addr_r_");
 235                     pw.println("    , dram_addr_a");
 236                     pw.println("    , dram_isread_");
 237                     pw.println("    , dram_write_data_");
 238                     pw.println("    , dram_write_data_push_");
 239                     pw.println("    , dram_write_data_full");
 240                     pw.println("    , dram_read_data");
 241                     pw.println("    , dram_read_data_pop_");
 242                     pw.println("    , dram_read_data_empty");
 243                     pw.println("    , dram_read_data_latency");
 244                 }
 245                 if (filename.equals("video")) {
 246                     pw.println("    , vga_clk");
 247                     pw.println("    , vga_psave");
 248                     pw.println("    , vga_hsync");
 249                     pw.println("    , vga_vsync");
 250                     pw.println("    , vga_sync");
 251                     pw.println("    , vga_blank");
 252                     pw.println("    , vga_r");
 253                     pw.println("    , vga_g");
 254                     pw.println("    , vga_b");
 255                     pw.println("    , vga_clkout");
 256                 }
 257                 pw.println("        );");
 258                 pw.println();
 259                 pw.println("    input clk;");
 260                 pw.println("    input rst;");
 261                 if (filename.equals("dram")) {
 262                     pw.println("output  [31:0] dram_addr_;");
 263                     pw.println("output         dram_addr_r_;");
 264                     pw.println("input          dram_addr_a;");
 265                     pw.println("output         dram_isread_;");
 266                     pw.println("output  [63:0] dram_write_data_;");
 267                     pw.println("output         dram_write_data_push_;");
 268                     pw.println("input          dram_write_data_full;");
 269                     pw.println("input   [63:0] dram_read_data;");
 270                     pw.println("output         dram_read_data_pop_;");
 271                     pw.println("input          dram_read_data_empty;");
 272                     pw.println("input   [1:0]  dram_read_data_latency;");
 273                 }
 274                 if (filename.equals("video")) {
 275                     pw.println("input          vga_clk;");
 276                     pw.println("output         vga_psave;");
 277                     pw.println("output         vga_hsync;");
 278                     pw.println("output         vga_vsync;");
 279                     pw.println("output         vga_sync;");
 280                     pw.println("output         vga_blank;");
 281                     pw.println("output   [7:0] vga_r;");
 282                     pw.println("output   [7:0] vga_g;");
 283                     pw.println("output   [7:0] vga_b;");
 284                     pw.println("output         vga_clkout;");
 285                 }
 286                 for(DockDescription bb : sd) {
 287                     String bb_name = bb.getName();
 288                     pw.print("        ");
 289                     if ("fifo".equals(filename)) continue;
 290                     if (bb.isInputDock()) {
 291                         pw.println("`input(" +
 292                                    bb_name+"_r,  "+
 293                                    bb_name+"_a,  "+
 294                                    bb_name+"_a_, "+
 295                                    "[("+WIDTH_WORD+"-1):0],"+
 296                                    bb_name+"_d)"
 297                                    );
 298                     } else {
 299                         pw.println("`output(" +
 300                                    bb_name+"_r,  "+
 301                                    bb_name+"_r_, "+
 302                                    bb_name+"_a,  "+
 303                                    "[("+WIDTH_WORD+"):0],"+
 304                                    bb_name+"_d_)"
 305                                    );
 306                         /*
 307                         if (!bb_name.equals("out") || !"memory".equals(filename))
 308                             pw.println("`defreg(" +
 309                                        bb_name+"_d_,  "+
 310                                        "[("+WIDTH_WORD+"-1):0],"+
 311                                        bb_name+"_d)"
 312                                        );
 313                         */
 314                     }
 315                     pw.println();
 316                 }
 317             }
 318
 319             pw.println(sd.getSection("fpga"));
 320
 321             if (auto)
 322                 pw.println("endmodule");
 323
 324             pw.flush();
 325             pw.close();
 326         } catch (Exception e) { throw new RuntimeException(e); }
 327     }
 328
 329     public long getDestAddr(Path path) {
 330         return ((FpgaPath)path).toLong();
 331     }
 332     public Dock getBoxByInstAddr(long dest) {
 333         for(Ship ship : Fpga.this)
 334             for(Dock bb : ship)
 335                 if (((FpgaDestination)((FpgaDock)bb).getInstructionDestination()).getAddr() == dest)
 336                     return bb;
 337         return null;
 338     }
 339
 340 }