1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.fpga.*;
3 import edu.berkeley.fleet.api.*;
4 import edu.berkeley.fleet.two.*;
5 import edu.berkeley.fleet.*;
6 import java.lang.reflect.*;
7 import edu.berkeley.sbp.chr.*;
8 import edu.berkeley.sbp.misc.*;
9 import edu.berkeley.sbp.meta.*;
10 import edu.berkeley.sbp.util.*;
13 import edu.berkeley.fleet.two.*;
14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
16 import static edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
19 public class Fpga extends FleetTwoFleet {
22 public FabricElement top_horn;
25 public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
26 public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
28 public Ship getShip(String type, int ordinal) {
30 if (s.getType().equals(type))
36 public static void main(String[] s) throws Exception {
37 new Fpga(new Module("main")).top.dump(s[0]);
40 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
41 pw.println("`timescale 1ns / 10ps");
44 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
45 pw.println("`define BRAM_ADDR_WIDTH 14");
46 pw.println("`define BRAM_DATA_WIDTH `WORDWIDTH");
47 pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
48 pw.println("`define BRAM_NAME bram14");
49 pw.println("`include \"bram.inc\"");
52 pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
53 pw.println("`define BRAM_ADDR_WIDTH 19");
54 pw.println("`define BRAM_DATA_WIDTH 3");
55 pw.println("`define BRAM_SIZE (640*480)");
56 pw.println("`define BRAM_NAME vram");
57 pw.println("`include \"bram.inc\"");
61 public Module getVerilogModule() { return top; }
63 public FleetProcess run(Instruction[] instructions) {
65 return new Client(this, "none", instructions);
66 } catch (Exception e) { throw new RuntimeException(e); }
69 public BitVector getDestAddr(Path path) {
70 return ((FpgaPath)path).toBitVector();
73 // Setup //////////////////////////////////////////////////////////////////////////////
75 public Ship createShip(String type, String name) throws IOException {
76 ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
77 FpgaShip ship = new FpgaShip(this, sd);
78 ships.put(name, ship);
82 public Fpga() throws Exception { this(new Module("main")); }
83 public Fpga(Module top) throws Exception {
85 debugShip = createShip("Debug", "debug");
87 //boolean small = false;
90 createShip("Memory", "memory1");
93 for(int i=0; i<2; i++)
94 createShip("Fifo", "fifo"+i);
95 for(int i=0; i<2; i++)
96 createShip("Alu", "alu"+i);
97 createShip("Counter", "counter");
98 createShip("CarrySaveAdder", "csa1");
99 createShip("Rotator", "rotator");
100 createShip("Lut3", "lut");
102 createShip("Memory", "memory2");
103 createShip("Memory", "memory3");
105 for(int i=0; i<3; i++)
106 createShip("Alu", "alu"+i);
108 for(int i=0; i<1; i++)
109 createShip("Fifo", "fifo"+i);
111 for(int i=0; i<14; i++)
112 createShip("Counter", "counter"+i);
115 createShip("CarrySaveAdder", "csa1");
116 createShip("Rotator", "rotator");
117 createShip("Lut3", "lut");
119 //createShip("DDR2", "ddr2");
121 createShip("DRAM", "dram");
122 createShip("Video", "video");
125 new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
127 Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET);
128 Module.Latch count = top.new Latch("count", 8);
130 ArrayList inbox_sources = new ArrayList<FabricElement>();
131 ArrayList inbox_dests = new ArrayList<FabricElement>();
132 ArrayList outbox_sources = new ArrayList<FabricElement>();
133 ArrayList outbox_dests = new ArrayList<FabricElement>();
134 ArrayList instruction_dests = new ArrayList<FabricElement>();
136 for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
137 for(Dock port : ship) {
138 if (port.isInputDock()) {
139 inbox_sources.add(((FpgaDock)port));
140 instruction_dests.add(port.getInstructionDestination());
141 inbox_dests.add(port.getDataDestination());
143 outbox_sources.add(((FpgaDock)port));
144 instruction_dests.add(port.getInstructionDestination());
145 outbox_dests.add(port.getDataDestination());
150 ArrayList dests = new ArrayList<FabricElement>();
151 ArrayList sources = new ArrayList<FabricElement>();
152 sources.addAll(inbox_sources);
153 sources.addAll(outbox_sources);
154 dests.addAll(inbox_dests);
155 dests.addAll(instruction_dests);
156 dests.addAll(outbox_dests);
157 top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
158 FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
159 FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
160 ((FunnelModule.FunnelInstance)source).out = top_funnel;
161 top_funnel.addOutput(top_horn, top_horn.getInputPort());
162 Module.SinkPort debug_in = top_funnel.getInputPort("in1");
164 top.addPreCrap("reg root_in_a_;");
165 top.addPreCrap("assign root_in_a = root_in_a_;");
166 top.new Event(new Object[] { "(root_in_r && root_in_a)" },
167 new Object[] { new SimpleAction("root_in_a_<=0;") });
168 top.new Event(new Object[] { "(root_in_r && !root_in_a)", "count<=7" },
169 new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], root_in_d[7:0] };"),
170 new AssignAction(count, count.getVerilogName()+"+1"),
171 new SimpleAction("root_in_a_<=1;")
173 top.new Event(new Object[] { debug_in, "count>7" },
174 new Object[] { new AssignAction(count, "0"),
175 new AssignAction(debug_in, temp_in),
180 public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
181 public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
184 case 1: return ports[start];
186 FabricElement leftPort = mkNode(ports, is_horn, start, (end+start)/2);
187 FabricElement rightPort = mkNode(ports, is_horn, (end+start)/2, end);
189 ? new HornModule.HornInstance(this, top, leftPort, rightPort)
190 : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
196 // Expand //////////////////////////////////////////////////////////////////////////////
198 public void expand(ShipDescription sd) {
200 if (sd.getSection("fpga")==null) return;
201 String filename = sd.getName().toLowerCase();
202 File outf = new File("build/fpga/"+filename+".v");
203 new File(outf.getParent()).mkdirs();
204 System.err.println("writing to " + outf);
205 FileOutputStream out = new FileOutputStream(outf);
206 PrintWriter pw = new PrintWriter(out);
208 pw.println("`define WORDWIDTH "+WIDTH_WORD);
209 pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
212 for(DockDescription dd : sd) {
213 String name = dd.getName();
214 pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
215 pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
216 if (dd.isInputDock()) {
217 pw.println("`define drain_"+name+" "+name+"_a <= 1;");
219 pw.println("`define fill_"+name+" "+name+"_r <= 1;");
220 pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
224 pw.print("`define reset ");
225 for(DockDescription bb : sd) {
226 String bb_name = bb.getName();
227 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
228 else pw.print(bb_name+"_r <= 0; ");
232 pw.print("`define cleanup ");
233 for(DockDescription bb : sd) {
234 String bb_name = bb.getName();
235 if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
236 else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
240 // FIXME: this corresponds to something
242 pw.print("`define flush_happening (1");
243 for(DockDescription bb : sd)
244 if (bb.isInputDock())
245 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]");
249 pw.print("`define flush ");
250 for(DockDescription bb : sd)
251 if (bb.isInputDock())
252 pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
254 for(DockDescription bb : sd)
255 if (bb.isInputDock())
256 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
257 pw.print(") begin ");
260 for(DockDescription bb : sd)
261 if (bb.isInputDock())
262 pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
263 pw.print(") begin ");
265 for(DockDescription bb : sd)
266 if (bb.isInputDock())
267 pw.print(bb.getName()+"_f <= 1; ");
269 pw.print(" end else if (0");
270 for(DockDescription bb : sd)
271 if (bb.isInputDock())
272 pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
273 pw.print(") begin ");
275 for(DockDescription bb : sd)
276 if (bb.isInputDock())
277 pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
284 pw.println("module " + filename + "( clk, rst ");
285 for(DockDescription bb : sd) {
286 String bb_name = bb.getName();
288 if (bb.isInputDock()) {
289 pw.print(", " + bb_name+"_r_");
290 pw.print(", " + bb_name+"_a_");
291 pw.print(", " + bb_name+"_d");
293 pw.print(", " + bb_name+"_r_");
294 pw.print(", " + bb_name+"_a");
295 pw.print(", " + bb_name+"_d_");
299 for(PercolatedPort pp : sd.percolatedPorts) {
305 pw.println(" input clk;");
306 pw.println(" input rst;");
307 for(PercolatedPort pp : sd.percolatedPorts) {
309 case UP: pw.print("output"); break;
310 case DOWN: pw.print("input"); break;
311 case INOUT: pw.print("inout"); break;
315 pw.print("["+(pp.width-1)+":0]");
321 for(DockDescription bb : sd) {
322 String bb_name = bb.getName();
323 if (bb.isInputDock()) {
324 pw.println(" input ["+WIDTH_WORD+":0] "+bb_name+"_d;");
325 pw.println(" input "+bb_name+"_r_;");
326 pw.println(" wire "+bb_name+"_r;");
327 pw.println(" assign "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
328 pw.println(" output "+bb_name+"_a_;");
329 pw.println(" reg "+bb_name+"_a;");
330 pw.println(" initial "+bb_name+"_a = 0;");
331 pw.println(" reg "+bb_name+"_f;");
332 pw.println(" initial "+bb_name+"_f = 0;");
333 pw.println(" assign "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
335 pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
336 pw.println(" input "+bb_name+"_a;");
337 pw.println(" output "+bb_name+"_r_;");
338 pw.println(" reg "+bb_name+"_r;");
339 pw.println(" initial "+bb_name+"_r = 0;");
340 pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
345 if (filename.equals("fifo")) {
346 pw.println(" wire in_a__;");
347 pw.println(" wire out_r__;");
348 pw.println(" fifo8x37 fifo8x37(clk, rst,");
349 pw.println(" in_r, in_a__, in_d,");
350 pw.println(" out_r__, out_a, out_d_);");
351 pw.println(" always @(posedge clk) begin");
352 pw.println(" if (!rst) begin");
353 pw.println(" `reset");
354 pw.println(" end else begin");
355 pw.println(" `flush");
356 pw.println(" out_r <= out_r__;");
357 pw.println(" in_a <= in_a__;");
361 pw.println(sd.getSection("fpga"));
364 pw.println("endmodule");
368 } catch (Exception e) { throw new RuntimeException(e); }