change small Fpga configuration to have one of each ship
[fleet.git] / src / edu / berkeley / fleet / fpga / Fpga.java
1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.fpga.*;
3 import edu.berkeley.fleet.api.*;
4 import edu.berkeley.fleet.two.*;
5 import edu.berkeley.fleet.*;
6 import java.lang.reflect.*;
7 import edu.berkeley.sbp.chr.*;
8 import edu.berkeley.sbp.misc.*;
9 import edu.berkeley.sbp.meta.*;
10 import edu.berkeley.sbp.util.*;
11 import java.util.*;
12 import java.io.*;
13 import edu.berkeley.fleet.two.*;
14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
16
17
18 /*
19 => get rid of getInputPort(String) and instead use members
20 => clean up fabricelement methods
21 => get rid of addcrap
22 => automatic width-setting on ports
23 => nuke DATAWIDTH?
24   => serdes and fastclock/slowclock?
25 */
26
27 public class Fpga extends FleetTwoFleet {
28
29     public  Module top;
30     public  FabricElement top_horn;
31     Ship debugShip;
32
33     public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
34     public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
35
36     public Ship getShip(String type, int ordinal) {
37         for(Ship s : this)
38             if (s.getType().equals(type))
39                 if (--ordinal < 0)
40                     return s;
41         return null;
42     }
43
44     public static void main(String[] s) throws Exception { 
45         new Fpga(new Module("root")).top.dump(s[0]);
46     }
47
48     public FleetProcess run(Instruction[] instructions) {
49         try {
50             return new Client(this, "none", instructions);
51         } catch (Exception e) { throw new RuntimeException(e); }
52     }
53
54     // Setup //////////////////////////////////////////////////////////////////////////////
55
56     public Ship createShip(String type, String name) throws IOException {
57         ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
58         FpgaShip ship = new FpgaShip(this, sd);
59         ships.put(name, ship);
60         return ship;
61     }
62
63     public Fpga() throws Exception { this(new Module("root")); }
64     public Fpga(Module top) throws Exception {
65         this.top = top;
66         debugShip = createShip("Debug",     "debug");
67
68         boolean small = false;
69
70         createShip("Memory",      "memory1");
71
72         if (small) {
73             createShip("Fifo",           "fifo");
74             createShip("Alu",            "alu");
75             createShip("Counter",        "counter");
76             createShip("CarrySaveAdder", "csa1");
77             createShip("Rotator",        "rotator");
78             createShip("Lut3",           "lut");
79         } else {
80             //createShip("Memory",    "memory2");
81             //createShip("Memory",    "memory3");
82
83             for(int i=0; i<5; i++)
84                 createShip("Alu",       "alu"+i);
85
86             for(int i=0; i<2; i++)
87                 createShip("Fifo",      "fifo"+i);
88
89             for(int i=0; i<13; i++)
90                 createShip("Counter",  "counter"+i);
91
92             createShip("CarrySaveAdder",  "csa1");
93             createShip("Rotator",         "rotator");
94             createShip("Lut3",            "lut");
95
96             //createShip("DDR2",    "ddr2");
97         }
98         createShip("DRAM",    "dram");
99         createShip("Video",   "video");
100
101         //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
102         Module.SourcePort  debug_out   = null;
103         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
104             if (ship.getType().toLowerCase().equals("debug"))
105                 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
106         }
107
108         // for FifoShip
109         new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
110
111         Module.SourcePort  in          = top.createInputPort("in", 8);
112         Module.SinkPort    out         = top.createOutputPort("out", 8, "");
113         Module.Latch       temp_in     = top.new Latch("temp", WIDTH_PACKET);
114         Module.Latch       count       = top.new Latch("count", 8);
115         Module.Latch       count_out   = top.new Latch("count_out", 8);
116
117         ArrayList inbox_sources = new ArrayList<FabricElement>();
118         ArrayList inbox_dests   = new ArrayList<FabricElement>();
119         ArrayList outbox_sources = new ArrayList<FabricElement>();
120         ArrayList outbox_dests   = new ArrayList<FabricElement>();
121         ArrayList instruction_dests   = new ArrayList<FabricElement>();
122         int numdocks = 0;
123         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
124             if (ship.getType().toLowerCase().equals("debug"))
125                 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
126             for(Dock port : ship) {
127                 if (port.isInputDock()) {
128                     inbox_sources.add(((FpgaDock)port));
129                     instruction_dests.add(port.getInstructionDestination());
130                     inbox_dests.add(port.getDataDestination());
131                 } else {
132                     outbox_sources.add(((FpgaDock)port));
133                     instruction_dests.add(port.getInstructionDestination());
134                     outbox_dests.add(port.getDataDestination());
135                 }
136                 numdocks++;
137             }
138         }
139         //System.err.println("dock count = " + numdocks);
140         ArrayList dests   = new ArrayList<FabricElement>();
141         ArrayList sources = new ArrayList<FabricElement>();
142         sources.addAll(inbox_sources);
143         sources.addAll(outbox_sources);
144         dests.addAll(inbox_dests);
145         dests.addAll(instruction_dests);
146         dests.addAll(outbox_dests);
147         top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
148         FabricElement   source  = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
149         FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
150         ((FunnelModule.FunnelInstance)source).out = top_funnel;
151         //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
152         top_funnel.addOutput(top_horn, top_horn.getInputPort());
153
154         //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
155         Module.SinkPort debug_in = top_funnel.getInputPort("in1");
156
157         top.new Event(new Object[] { in, "count<=7" },
158                       new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
159                                      new SimpleAction("count <= count+1;"),
160                                      in
161                       });
162         top.new Event(new Object[] { debug_in, "count>7" },
163                       new Object[] { new SimpleAction(" count <= 0; "),
164                                      new AssignAction(debug_in, temp_in),
165                                      debug_in
166                       });
167         top.new Event(new Object[] { out, debug_out },
168                       new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
169                                      new SimpleAction("if (count_out >= 5) begin "+
170                                                           "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
171                                                           " else count_out <= count_out+1; "),
172                                      out });
173
174     }
175
176     public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
177     public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
178         switch(end-start) {
179             case 0: return null;
180             case 1: return ports[start];
181             default: {
182                 FabricElement leftPort  = mkNode(ports, is_horn,  start,         (end+start)/2);
183                 FabricElement rightPort = mkNode(ports, is_horn,  (end+start)/2, end);
184                 return is_horn
185                     ? new HornModule.HornInstance(this, top,     leftPort, rightPort)
186                     : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
187             }
188         }
189     }
190
191     public Module getVerilogModule() { return top; }
192
193
194     // Expand //////////////////////////////////////////////////////////////////////////////
195
196     public void expand(ShipDescription sd) {
197         try {
198             if (sd.getSection("fpga")==null) return;
199             String filename = sd.getName().toLowerCase();
200             File outf = new File("build/fpga/"+filename+".v");
201             new File(outf.getParent()).mkdirs();
202             System.err.println("writing to " + outf);
203             FileOutputStream out = new FileOutputStream(outf);
204             PrintWriter pw = new PrintWriter(out);
205
206             boolean debug = "debug".equals(filename);
207
208             pw.println("`define DATAWIDTH                "+WIDTH_WORD);
209             pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
210             pw.println();
211
212             for(DockDescription dd : sd) {
213                 String name = dd.getName();
214                 pw.println("`define "+name+"_full    ("+name+"_r && !"+name+"_a)");
215                 pw.println("`define "+name+"_empty  (!"+name+"_r && !"+name+"_a)");
216                 if (dd.isInputDock()) {
217                     pw.println("`define drain_"+name+"  "+name+"_a <= 1");
218                 } else {
219                     pw.println("`define fill_"+name+"  "+name+"_r <= 1");
220                 }
221             }
222
223             pw.print("`define reset ");
224             for(DockDescription bb : sd) {
225                 String bb_name = bb.getName();
226                 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
227                 else                  pw.print(bb_name+"_r <= 0; ");
228             }
229             pw.println();
230
231             pw.print("`define flush ");
232             for(DockDescription bb : sd)
233                 if (bb.isInputDock())
234                     pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
235             pw.print("if (1");
236             for(DockDescription bb : sd)
237                 if (bb.isInputDock())
238                     pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
239             pw.print(") begin ");
240             if (true) {
241                 pw.print("if (1");
242                 for(DockDescription bb : sd)
243                     if (bb.isInputDock())
244                         pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
245                 pw.print(") begin ");
246                 if (true) {
247                     for(DockDescription bb : sd)
248                         if (bb.isInputDock())
249                             pw.print(bb.getName()+"_f <= 1; ");
250                 }
251                 pw.print(" end else if (0");
252                 for(DockDescription bb : sd)
253                     if (bb.isInputDock())
254                         pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
255                 pw.print(") begin ");
256                 if (true) {
257                     for(DockDescription bb : sd)
258                         if (bb.isInputDock())
259                             pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
260                 }
261                 pw.print(" end ");
262             }
263             pw.print(" end ");
264             pw.println();
265             
266             pw.println("module " + filename + "( clk, rst ");
267             for(DockDescription bb : sd) {
268                 String bb_name = bb.getName();
269                 pw.print("        ");
270                 if (bb.isInputDock()) {
271                     pw.print(", " + bb_name+"_r_");
272                     pw.print(", " + bb_name+"_a_");
273                     pw.print(", " + bb_name+"_d");
274                 } else {
275                     pw.print(", " + bb_name+"_r_");
276                     pw.print(", " + bb_name+"_a");
277                     pw.print(", " + bb_name+"_d_");
278                 }
279                 pw.println();
280             }
281             if (filename.equals("debug")) {
282                 pw.println("    , out_r_");
283                 pw.println("    , out_a");
284                 pw.println("    , out_d_");
285             }
286             if (filename.equals("dram")) {
287                 pw.println("    , dram_addr_");
288                 pw.println("    , dram_addr_r_");
289                 pw.println("    , dram_addr_a");
290                 pw.println("    , dram_isread_");
291                 pw.println("    , dram_write_data_");
292                 pw.println("    , dram_write_data_push_");
293                 pw.println("    , dram_write_data_full");
294                 pw.println("    , dram_read_data");
295                 pw.println("    , dram_read_data_pop_");
296                 pw.println("    , dram_read_data_empty");
297                 pw.println("    , dram_read_data_latency");
298             }
299             if (filename.equals("ddr2")) {
300                 pw.println("    , ddr2_addr_");
301                 pw.println("    , ddr2_addr_r_");
302                 pw.println("    , ddr2_addr_a");
303                 pw.println("    , ddr2_isread_");
304                 pw.println("    , ddr2_write_data_");
305                 pw.println("    , ddr2_write_data_push_");
306                 pw.println("    , ddr2_write_data_full");
307                 pw.println("    , ddr2_read_data");
308                 pw.println("    , ddr2_read_data_pop_");
309                 pw.println("    , ddr2_read_data_empty");
310                 pw.println("    , ddr2_read_data_latency");
311             }
312             if (filename.equals("video")) {
313                 pw.println("    , vga_clk");
314                 pw.println("    , vga_psave");
315                 pw.println("    , vga_hsync");
316                 pw.println("    , vga_vsync");
317                 pw.println("    , vga_sync");
318                 pw.println("    , vga_blank");
319                 pw.println("    , vga_r");
320                 pw.println("    , vga_g");
321                 pw.println("    , vga_b");
322                 pw.println("    , vga_clkout");
323             }
324             pw.println("        );");
325             pw.println();
326             pw.println("    input clk;");
327             pw.println("    input rst;");
328             if (filename.equals("debug")) {
329                 pw.println("        output  ["+WIDTH_WORD+":0] out_d_;");
330                 pw.println("        input   out_a;");
331                 pw.println("        output  out_r_;");
332             }
333             if (filename.equals("dram")) {
334                 pw.println("output  [31:0] dram_addr_;");
335                 pw.println("output         dram_addr_r_;");
336                 pw.println("input          dram_addr_a;");
337                 pw.println("output         dram_isread_;");
338                 pw.println("output  [63:0] dram_write_data_;");
339                 pw.println("output         dram_write_data_push_;");
340                 pw.println("input          dram_write_data_full;");
341                 pw.println("input   [63:0] dram_read_data;");
342                 pw.println("output         dram_read_data_pop_;");
343                 pw.println("input          dram_read_data_empty;");
344                 pw.println("input   [1:0]  dram_read_data_latency;");
345             }
346             if (filename.equals("ddr2")) {
347                 pw.println("output  [31:0] ddr2_addr_;");
348                 pw.println("output         ddr2_addr_r_;");
349                 pw.println("input          ddr2_addr_a;");
350                 pw.println("output         ddr2_isread_;");
351                 pw.println("output  [63:0] ddr2_write_data_;");
352                 pw.println("output         ddr2_write_data_push_;");
353                 pw.println("input          ddr2_write_data_full;");
354                 pw.println("input   [63:0] ddr2_read_data;");
355                 pw.println("output         ddr2_read_data_pop_;");
356                 pw.println("input          ddr2_read_data_empty;");
357                 pw.println("input   [1:0]  ddr2_read_data_latency;");
358             }
359             if (filename.equals("video")) {
360                 pw.println("input          vga_clk;");
361                 pw.println("output         vga_psave;");
362                 pw.println("output         vga_hsync;");
363                 pw.println("output         vga_vsync;");
364                 pw.println("output         vga_sync;");
365                 pw.println("output         vga_blank;");
366                 pw.println("output   [7:0] vga_r;");
367                 pw.println("output   [7:0] vga_g;");
368                 pw.println("output   [7:0] vga_b;");
369                 pw.println("output         vga_clkout;");
370             }
371
372             for(DockDescription bb : sd) {
373                 String bb_name = bb.getName();
374                 if (bb.isInputDock()) {
375                     pw.println("        input   ["+WIDTH_WORD+":0] "+bb_name+"_d;");
376                     pw.println("        input   "+bb_name+"_r_;");
377                     pw.println("        wire    "+bb_name+"_r;");
378                     pw.println("        assign  "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
379                     pw.println("        output  "+bb_name+"_a_;");
380                     pw.println("        reg     "+bb_name+"_a;");
381                     pw.println("        initial "+bb_name+"_a  = 0;");
382                     pw.println("        reg     "+bb_name+"_f;");
383                     pw.println("        initial "+bb_name+"_f  = 0;");
384                     pw.println("        assign  "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
385                 } else {
386                     pw.println("        output  ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
387                     pw.println("        input   "+bb_name+"_a;");
388                     pw.println("        output  "+bb_name+"_r_;");
389                     pw.println("        reg     "+bb_name+"_r;");
390                     pw.println("        initial "+bb_name+"_r  = 0;");
391                     pw.println("        assign  "+bb_name+"_r_ = "+bb_name+"_r;");
392                 }
393                 pw.println();
394             }
395
396             pw.println(sd.getSection("fpga"));
397
398             pw.println("endmodule");
399
400             pw.flush();
401             pw.close();
402         } catch (Exception e) { throw new RuntimeException(e); }
403     }
404
405     public long getDestAddr(Path path) {
406         return ((FpgaPath)path).toLong();
407     }
408     public Dock getBoxByInstAddr(long dest) {
409         for(Ship ship : Fpga.this)
410             for(Dock bb : ship)
411                 if (((FpgaDestination)((FpgaDock)bb).getInstructionDestination()).getAddr() == dest)
412                     return bb;
413         return null;
414     }
415
416 }