1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.fpga.*;
3 import edu.berkeley.fleet.api.*;
4 import edu.berkeley.fleet.two.*;
5 import edu.berkeley.fleet.*;
6 import java.lang.reflect.*;
7 import edu.berkeley.sbp.chr.*;
8 import edu.berkeley.sbp.misc.*;
9 import edu.berkeley.sbp.meta.*;
10 import edu.berkeley.sbp.util.*;
13 import edu.berkeley.fleet.two.*;
14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
19 => get rid of getInputPort(String) and instead use members
20 => clean up fabricelement methods
22 => automatic width-setting on ports
24 => serdes and fastclock/slowclock?
27 public class Fpga extends FleetTwoFleet {
30 public FabricElement top_horn;
33 public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
34 public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
36 public Ship getShip(String type, int ordinal) {
38 if (s.getType().equals(type))
44 public static void main(String[] s) throws Exception {
45 new Fpga(new Module("root")).top.dump(s[0]);
48 public Module getVerilogModule() { return top; }
50 public FleetProcess run(Instruction[] instructions) {
52 return new Client(this, "none", instructions);
53 } catch (Exception e) { throw new RuntimeException(e); }
56 public BitVector getDestAddr(Path path) {
57 return ((FpgaPath)path).toBitVector();
60 // Setup //////////////////////////////////////////////////////////////////////////////
62 public Ship createShip(String type, String name) throws IOException {
63 ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
64 FpgaShip ship = new FpgaShip(this, sd);
65 ships.put(name, ship);
69 public Fpga() throws Exception { this(new Module("root")); }
70 public Fpga(Module top) throws Exception {
72 debugShip = createShip("Debug", "debug");
74 boolean small = false;
76 createShip("Memory", "memory1");
79 createShip("Fifo", "fifo");
80 createShip("Alu", "alu");
81 createShip("Counter", "counter");
82 createShip("CarrySaveAdder", "csa1");
83 createShip("Rotator", "rotator");
84 createShip("Lut3", "lut");
86 createShip("Memory", "memory2");
87 createShip("Memory", "memory3");
89 for(int i=0; i<5; i++)
90 createShip("Alu", "alu"+i);
92 for(int i=0; i<2; i++)
93 createShip("Fifo", "fifo"+i);
95 for(int i=0; i<13; i++)
96 createShip("Counter", "counter"+i);
98 createShip("CarrySaveAdder", "csa1");
99 createShip("Rotator", "rotator");
100 createShip("Lut3", "lut");
102 //createShip("DDR2", "ddr2");
104 createShip("DRAM", "dram");
105 createShip("Video", "video");
107 //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
108 Module.SourcePort debug_out = null;
109 for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
110 if (ship.getType().toLowerCase().equals("debug"))
111 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
115 new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
117 Module.SourcePort in = top.createInputPort("in", 8);
118 Module.SinkPort out = top.createOutputPort("out", 8, "");
119 Module.Latch temp_in = top.new Latch("temp", WIDTH_PACKET);
120 Module.Latch count = top.new Latch("count", 8);
121 Module.Latch count_out = top.new Latch("count_out", 8);
123 ArrayList inbox_sources = new ArrayList<FabricElement>();
124 ArrayList inbox_dests = new ArrayList<FabricElement>();
125 ArrayList outbox_sources = new ArrayList<FabricElement>();
126 ArrayList outbox_dests = new ArrayList<FabricElement>();
127 ArrayList instruction_dests = new ArrayList<FabricElement>();
129 for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
130 if (ship.getType().toLowerCase().equals("debug"))
131 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
132 for(Dock port : ship) {
133 if (port.isInputDock()) {
134 inbox_sources.add(((FpgaDock)port));
135 instruction_dests.add(port.getInstructionDestination());
136 inbox_dests.add(port.getDataDestination());
138 outbox_sources.add(((FpgaDock)port));
139 instruction_dests.add(port.getInstructionDestination());
140 outbox_dests.add(port.getDataDestination());
145 //System.err.println("dock count = " + numdocks);
146 ArrayList dests = new ArrayList<FabricElement>();
147 ArrayList sources = new ArrayList<FabricElement>();
148 sources.addAll(inbox_sources);
149 sources.addAll(outbox_sources);
150 dests.addAll(inbox_dests);
151 dests.addAll(instruction_dests);
152 dests.addAll(outbox_dests);
153 top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
154 FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
155 FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
156 ((FunnelModule.FunnelInstance)source).out = top_funnel;
157 //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
158 top_funnel.addOutput(top_horn, top_horn.getInputPort());
160 //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
161 Module.SinkPort debug_in = top_funnel.getInputPort("in1");
163 top.new Event(new Object[] { in, "count<=7" },
164 new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
165 new SimpleAction("count <= count+1;"),
168 top.new Event(new Object[] { debug_in, "count>7" },
169 new Object[] { new SimpleAction(" count <= 0; "),
170 new AssignAction(debug_in, temp_in),
173 top.new Event(new Object[] { out, debug_out },
174 new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
175 new SimpleAction("if (count_out >= 5) begin "+
176 "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
177 " else count_out <= count_out+1; "),
182 public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
183 public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
186 case 1: return ports[start];
188 FabricElement leftPort = mkNode(ports, is_horn, start, (end+start)/2);
189 FabricElement rightPort = mkNode(ports, is_horn, (end+start)/2, end);
191 ? new HornModule.HornInstance(this, top, leftPort, rightPort)
192 : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
198 // Expand //////////////////////////////////////////////////////////////////////////////
200 public void expand(ShipDescription sd) {
202 if (sd.getSection("fpga")==null) return;
203 String filename = sd.getName().toLowerCase();
204 File outf = new File("build/fpga/"+filename+".v");
205 new File(outf.getParent()).mkdirs();
206 System.err.println("writing to " + outf);
207 FileOutputStream out = new FileOutputStream(outf);
208 PrintWriter pw = new PrintWriter(out);
210 boolean debug = "debug".equals(filename);
212 pw.println("`define DATAWIDTH "+WIDTH_WORD);
213 pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
216 for(DockDescription dd : sd) {
217 String name = dd.getName();
218 pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
219 pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
220 if (dd.isInputDock()) {
221 pw.println("`define drain_"+name+" "+name+"_a <= 1");
223 pw.println("`define fill_"+name+" "+name+"_r <= 1");
227 pw.print("`define reset ");
228 for(DockDescription bb : sd) {
229 String bb_name = bb.getName();
230 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
231 else pw.print(bb_name+"_r <= 0; ");
235 pw.print("`define flush ");
236 for(DockDescription bb : sd)
237 if (bb.isInputDock())
238 pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
240 for(DockDescription bb : sd)
241 if (bb.isInputDock())
242 pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
243 pw.print(") begin ");
246 for(DockDescription bb : sd)
247 if (bb.isInputDock())
248 pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
249 pw.print(") begin ");
251 for(DockDescription bb : sd)
252 if (bb.isInputDock())
253 pw.print(bb.getName()+"_f <= 1; ");
255 pw.print(" end else if (0");
256 for(DockDescription bb : sd)
257 if (bb.isInputDock())
258 pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
259 pw.print(") begin ");
261 for(DockDescription bb : sd)
262 if (bb.isInputDock())
263 pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
270 pw.println("module " + filename + "( clk, rst ");
271 for(DockDescription bb : sd) {
272 String bb_name = bb.getName();
274 if (bb.isInputDock()) {
275 pw.print(", " + bb_name+"_r_");
276 pw.print(", " + bb_name+"_a_");
277 pw.print(", " + bb_name+"_d");
279 pw.print(", " + bb_name+"_r_");
280 pw.print(", " + bb_name+"_a");
281 pw.print(", " + bb_name+"_d_");
285 if (filename.equals("debug")) {
286 pw.println(" , out_r_");
287 pw.println(" , out_a");
288 pw.println(" , out_d_");
290 if (filename.equals("dram")) {
291 pw.println(" , dram_addr_");
292 pw.println(" , dram_addr_r_");
293 pw.println(" , dram_addr_a");
294 pw.println(" , dram_isread_");
295 pw.println(" , dram_write_data_");
296 pw.println(" , dram_write_data_push_");
297 pw.println(" , dram_write_data_full");
298 pw.println(" , dram_read_data");
299 pw.println(" , dram_read_data_pop_");
300 pw.println(" , dram_read_data_empty");
301 pw.println(" , dram_read_data_latency");
303 if (filename.equals("ddr2")) {
304 pw.println(" , ddr2_addr_");
305 pw.println(" , ddr2_addr_r_");
306 pw.println(" , ddr2_addr_a");
307 pw.println(" , ddr2_isread_");
308 pw.println(" , ddr2_write_data_");
309 pw.println(" , ddr2_write_data_push_");
310 pw.println(" , ddr2_write_data_full");
311 pw.println(" , ddr2_read_data");
312 pw.println(" , ddr2_read_data_pop_");
313 pw.println(" , ddr2_read_data_empty");
314 pw.println(" , ddr2_read_data_latency");
316 if (filename.equals("video")) {
317 pw.println(" , vga_clk");
318 pw.println(" , vga_psave");
319 pw.println(" , vga_hsync");
320 pw.println(" , vga_vsync");
321 pw.println(" , vga_sync");
322 pw.println(" , vga_blank");
323 pw.println(" , vga_r");
324 pw.println(" , vga_g");
325 pw.println(" , vga_b");
326 pw.println(" , vga_clkout");
330 pw.println(" input clk;");
331 pw.println(" input rst;");
332 if (filename.equals("debug")) {
333 pw.println(" output ["+WIDTH_WORD+":0] out_d_;");
334 pw.println(" input out_a;");
335 pw.println(" output out_r_;");
337 if (filename.equals("dram")) {
338 pw.println("output [31:0] dram_addr_;");
339 pw.println("output dram_addr_r_;");
340 pw.println("input dram_addr_a;");
341 pw.println("output dram_isread_;");
342 pw.println("output [63:0] dram_write_data_;");
343 pw.println("output dram_write_data_push_;");
344 pw.println("input dram_write_data_full;");
345 pw.println("input [63:0] dram_read_data;");
346 pw.println("output dram_read_data_pop_;");
347 pw.println("input dram_read_data_empty;");
348 pw.println("input [1:0] dram_read_data_latency;");
350 if (filename.equals("ddr2")) {
351 pw.println("output [31:0] ddr2_addr_;");
352 pw.println("output ddr2_addr_r_;");
353 pw.println("input ddr2_addr_a;");
354 pw.println("output ddr2_isread_;");
355 pw.println("output [63:0] ddr2_write_data_;");
356 pw.println("output ddr2_write_data_push_;");
357 pw.println("input ddr2_write_data_full;");
358 pw.println("input [63:0] ddr2_read_data;");
359 pw.println("output ddr2_read_data_pop_;");
360 pw.println("input ddr2_read_data_empty;");
361 pw.println("input [1:0] ddr2_read_data_latency;");
363 if (filename.equals("video")) {
364 pw.println("input vga_clk;");
365 pw.println("output vga_psave;");
366 pw.println("output vga_hsync;");
367 pw.println("output vga_vsync;");
368 pw.println("output vga_sync;");
369 pw.println("output vga_blank;");
370 pw.println("output [7:0] vga_r;");
371 pw.println("output [7:0] vga_g;");
372 pw.println("output [7:0] vga_b;");
373 pw.println("output vga_clkout;");
376 for(DockDescription bb : sd) {
377 String bb_name = bb.getName();
378 if (bb.isInputDock()) {
379 pw.println(" input ["+WIDTH_WORD+":0] "+bb_name+"_d;");
380 pw.println(" input "+bb_name+"_r_;");
381 pw.println(" wire "+bb_name+"_r;");
382 pw.println(" assign "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
383 pw.println(" output "+bb_name+"_a_;");
384 pw.println(" reg "+bb_name+"_a;");
385 pw.println(" initial "+bb_name+"_a = 0;");
386 pw.println(" reg "+bb_name+"_f;");
387 pw.println(" initial "+bb_name+"_f = 0;");
388 pw.println(" assign "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
390 pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
391 pw.println(" input "+bb_name+"_a;");
392 pw.println(" output "+bb_name+"_r_;");
393 pw.println(" reg "+bb_name+"_r;");
394 pw.println(" initial "+bb_name+"_r = 0;");
395 pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
400 pw.println(sd.getSection("fpga"));
402 pw.println("endmodule");
406 } catch (Exception e) { throw new RuntimeException(e); }