src/edu/berkeley/fleet/fpga/Fpga.java

   1 package edu.berkeley.fleet.fpga;
   2 import edu.berkeley.fleet.fpga.*;
   3 import edu.berkeley.fleet.api.*;
   4 import edu.berkeley.fleet.two.*;
   5 import edu.berkeley.fleet.*;
   6 import java.lang.reflect.*;
   7 import edu.berkeley.sbp.chr.*;
   8 import edu.berkeley.sbp.misc.*;
   9 import edu.berkeley.sbp.meta.*;
  10 import edu.berkeley.sbp.util.*;
  11 import java.util.*;
  12 import java.io.*;
  13 import edu.berkeley.fleet.two.*;
  14 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
  15 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
  16
  17
  18 /*
  19 => get rid of getInputPort(String) and instead use members
  20 => clean up fabricelement methods
  21 => get rid of addcrap
  22 => automatic width-setting on ports
  23 => nuke DATAWIDTH?
  24   => serdes and fastclock/slowclock?
  25 */
  26
  27 public class Fpga extends FleetTwoFleet {
  28
  29     public  Module top;
  30     public  FabricElement top_horn;
  31     Ship debugShip;
  32
  33     public LinkedHashMap<String,FpgaShip> ships = new LinkedHashMap<String,FpgaShip>();
  34     public Iterator<Ship> iterator() { return (Iterator<Ship>)(Object)ships.values().iterator(); }
  35
  36     public Ship getShip(String type, int ordinal) {
  37         for(Ship s : this)
  38             if (s.getType().equals(type))
  39                 if (--ordinal < 0)
  40                     return s;
  41         return null;
  42     }
  43
  44     public static void main(String[] s) throws Exception {
  45         new Fpga(new Module("root")).top.dump(s[0]);
  46         PrintWriter pw;
  47
  48         pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
  49         pw.println("`timescale 1ns / 10ps");
  50         pw.close();
  51
  52         pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
  53         pw.println("`define BRAM_ADDR_WIDTH 14");
  54         pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
  55         pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
  56         pw.println("`define BRAM_NAME bram14");
  57         pw.println("`include \"bram.inc\"");
  58         pw.close();
  59
  60         pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
  61         pw.println("`define BRAM_ADDR_WIDTH 19");
  62         pw.println("`define BRAM_DATA_WIDTH 3");
  63         pw.println("`define BRAM_SIZE (640*480)");
  64         pw.println("`define BRAM_NAME vram");
  65         pw.println("`include \"bram.inc\"");
  66         pw.close();
  67     }
  68
  69     public Module getVerilogModule() { return top; }
  70
  71     public FleetProcess run(Instruction[] instructions) {
  72         try {
  73             return new Client(this, "none", instructions);
  74         } catch (Exception e) { throw new RuntimeException(e); }
  75     }
  76
  77     public BitVector getDestAddr(Path path) {
  78         return ((FpgaPath)path).toBitVector();
  79     }
  80
  81     // Setup //////////////////////////////////////////////////////////////////////////////
  82
  83     public Ship createShip(String type, String name) throws IOException {
  84         ShipDescription sd = new ShipDescription(type, new BufferedReader(new InputStreamReader(new FileInputStream("ships/"+type+".ship"))));
  85         FpgaShip ship = new FpgaShip(this, sd);
  86         ships.put(name, ship);
  87         return ship;
  88     }
  89
  90     public Fpga() throws Exception { this(new Module("root")); }
  91     public Fpga(Module top) throws Exception {
  92         this.top = top;
  93         debugShip = createShip("Debug",     "debug");
  94
  95         boolean small = false;
  96
  97         createShip("Memory",      "memory1");
  98
  99         if (small) {
 100             createShip("Fifo",           "fifo");
 101             createShip("Alu",            "alu");
 102             createShip("Counter",        "counter");
 103             createShip("CarrySaveAdder", "csa1");
 104             createShip("Rotator",        "rotator");
 105             createShip("Lut3",           "lut");
 106         } else {
 107             createShip("Memory",    "memory2");
 108             createShip("Memory",    "memory3");
 109
 110             for(int i=0; i<3; i++)
 111                 createShip("Alu",       "alu"+i);
 112
 113             /*
 114             for(int i=0; i<2; i++)
 115                 createShip("Fifo",      "fifo"+i);
 116             */
 117
 118             for(int i=0; i<14; i++)
 119                 createShip("Counter",  "counter"+i);
 120
 121             /*
 122             createShip("CarrySaveAdder",  "csa1");
 123             createShip("Rotator",         "rotator");
 124             createShip("Lut3",            "lut");
 125             */
 126             //createShip("DDR2",    "ddr2");
 127         }
 128         createShip("DRAM",    "dram");
 129         createShip("Video",   "video");
 130
 131         //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
 132         Module.SourcePort  debug_out   = null;
 133         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
 134             if (ship.getType().toLowerCase().equals("debug"))
 135                 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
 136         }
 137
 138         // for FifoShip
 139         new Module.InstantiatedModule(top, new FifoModule(8, WIDTH_WORD));
 140
 141         Module.SourcePort  in          = top.createInputPort("in", 8);
 142         Module.SinkPort    out         = top.createOutputPort("out", 8, "");
 143         Module.Latch       temp_in     = top.new Latch("temp", WIDTH_PACKET);
 144         Module.Latch       count       = top.new Latch("count", 8);
 145         Module.Latch       count_out   = top.new Latch("count_out", 8);
 146
 147         ArrayList inbox_sources = new ArrayList<FabricElement>();
 148         ArrayList inbox_dests   = new ArrayList<FabricElement>();
 149         ArrayList outbox_sources = new ArrayList<FabricElement>();
 150         ArrayList outbox_dests   = new ArrayList<FabricElement>();
 151         ArrayList instruction_dests   = new ArrayList<FabricElement>();
 152         int numdocks = 0;
 153         for(FpgaShip ship : (Iterable<FpgaShip>)(Object)this) {
 154             if (ship.getType().toLowerCase().equals("debug"))
 155                 debug_out = ship.getVerilogModule().getOutputPort("debug_out");
 156             for(Dock port : ship) {
 157                 if (port.isInputDock()) {
 158                     inbox_sources.add(((FpgaDock)port));
 159                     instruction_dests.add(port.getInstructionDestination());
 160                     inbox_dests.add(port.getDataDestination());
 161                 } else {
 162                     outbox_sources.add(((FpgaDock)port));
 163                     instruction_dests.add(port.getInstructionDestination());
 164                     outbox_dests.add(port.getDataDestination());
 165                 }
 166                 numdocks++;
 167             }
 168         }
 169         //System.err.println("dock count = " + numdocks);
 170         ArrayList dests   = new ArrayList<FabricElement>();
 171         ArrayList sources = new ArrayList<FabricElement>();
 172         sources.addAll(inbox_sources);
 173         sources.addAll(outbox_sources);
 174         dests.addAll(inbox_dests);
 175         dests.addAll(instruction_dests);
 176         dests.addAll(outbox_dests);
 177         top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
 178         FabricElement   source  = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
 179         FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
 180         ((FunnelModule.FunnelInstance)source).out = top_funnel;
 181         //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
 182         top_funnel.addOutput(top_horn, top_horn.getInputPort());
 183
 184         //Module.SourcePort  debug_in    = top.createWireSourcePort("debug_in", WIDTH_PACKET);
 185         Module.SinkPort debug_in = top_funnel.getInputPort("in1");
 186
 187         top.new Event(new Object[] { in, "count<=7" },
 188                       new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
 189                                      new SimpleAction("count <= count+1;"),
 190                                      in
 191                       });
 192         top.new Event(new Object[] { debug_in, "count>7" },
 193                       new Object[] { new SimpleAction(" count <= 0; "),
 194                                      new AssignAction(debug_in, temp_in),
 195                                      debug_in
 196                       });
 197         top.new Event(new Object[] { out, debug_out },
 198                       new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
 199                                      new SimpleAction("if (count_out >= 5) begin "+
 200                                                           "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
 201                                                           " else count_out <= count_out+1; "),
 202                                      out });
 203
 204     }
 205
 206     public FabricElement mkNode(FabricElement[] ports, boolean is_horn) { return mkNode(ports, is_horn, 0, ports.length); }
 207     public FabricElement mkNode(FabricElement[] ports, boolean is_horn, int start, int end) {
 208         switch(end-start) {
 209             case 0: return null;
 210             case 1: return ports[start];
 211             default: {
 212                 FabricElement leftPort  = mkNode(ports, is_horn,  start,         (end+start)/2);
 213                 FabricElement rightPort = mkNode(ports, is_horn,  (end+start)/2, end);
 214                 return is_horn
 215                     ? new HornModule.HornInstance(this, top,     leftPort, rightPort)
 216                     : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
 217             }
 218         }
 219     }
 220
 221
 222     // Expand //////////////////////////////////////////////////////////////////////////////
 223
 224     public void expand(ShipDescription sd) {
 225         try {
 226             if (sd.getSection("fpga")==null) return;
 227             String filename = sd.getName().toLowerCase();
 228             File outf = new File("build/fpga/"+filename+".v");
 229             new File(outf.getParent()).mkdirs();
 230             System.err.println("writing to " + outf);
 231             FileOutputStream out = new FileOutputStream(outf);
 232             PrintWriter pw = new PrintWriter(out);
 233
 234             boolean debug = "debug".equals(filename);
 235
 236             pw.println("`define DATAWIDTH                "+WIDTH_WORD);
 237             pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
 238             pw.println();
 239
 240             for(DockDescription dd : sd) {
 241                 String name = dd.getName();
 242                 pw.println("`define "+name+"_full    ("+name+"_r && !"+name+"_a)");
 243                 pw.println("`define "+name+"_empty  (!"+name+"_r && !"+name+"_a)");
 244                 if (dd.isInputDock()) {
 245                     pw.println("`define drain_"+name+"  "+name+"_a <= 1;");
 246                 } else {
 247                     pw.println("`define fill_"+name+"  "+name+"_r <= 1;");
 248                     pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
 249                 }
 250             }
 251
 252             pw.print("`define reset ");
 253             for(DockDescription bb : sd) {
 254                 String bb_name = bb.getName();
 255                 if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
 256                 else                  pw.print(bb_name+"_r <= 0; ");
 257             }
 258             pw.println();
 259
 260             pw.print("`define flush ");
 261             for(DockDescription bb : sd)
 262                 if (bb.isInputDock())
 263                     pw.print(" if (!"+bb.getName()+"_r_) "+bb.getName()+"_f <= 0; ");
 264             pw.print("if (1");
 265             for(DockDescription bb : sd)
 266                 if (bb.isInputDock())
 267                     pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a");
 268             pw.print(") begin ");
 269             if (true) {
 270                 pw.print("if (1");
 271                 for(DockDescription bb : sd)
 272                     if (bb.isInputDock())
 273                         pw.print(" && "+bb.getName()+"_d["+WIDTH_WORD+"] ");
 274                 pw.print(") begin ");
 275                 if (true) {
 276                     for(DockDescription bb : sd)
 277                         if (bb.isInputDock())
 278                             pw.print(bb.getName()+"_f <= 1; ");
 279                 }
 280                 pw.print(" end else if (0");
 281                 for(DockDescription bb : sd)
 282                     if (bb.isInputDock())
 283                         pw.print(" || "+bb.getName()+"_d["+WIDTH_WORD+"] ");
 284                 pw.print(") begin ");
 285                 if (true) {
 286                     for(DockDescription bb : sd)
 287                         if (bb.isInputDock())
 288                             pw.print(" if (!"+bb.getName()+"_d["+WIDTH_WORD+"]) "+bb.getName()+"_f <= 1; ");
 289                 }
 290                 pw.print(" end ");
 291             }
 292             pw.print(" end ");
 293             pw.println();
 294
 295             pw.println("module " + filename + "( clk, rst ");
 296             for(DockDescription bb : sd) {
 297                 String bb_name = bb.getName();
 298                 pw.print("        ");
 299                 if (bb.isInputDock()) {
 300                     pw.print(", " + bb_name+"_r_");
 301                     pw.print(", " + bb_name+"_a_");
 302                     pw.print(", " + bb_name+"_d");
 303                 } else {
 304                     pw.print(", " + bb_name+"_r_");
 305                     pw.print(", " + bb_name+"_a");
 306                     pw.print(", " + bb_name+"_d_");
 307                 }
 308                 pw.println();
 309             }
 310             if (filename.equals("debug")) {
 311                 pw.println("    , out_r_");
 312                 pw.println("    , out_a");
 313                 pw.println("    , out_d_");
 314             }
 315             if (filename.equals("dram")) {
 316                 pw.println("    , dram_addr_");
 317                 pw.println("    , dram_addr_r_");
 318                 pw.println("    , dram_addr_a");
 319                 pw.println("    , dram_isread_");
 320                 pw.println("    , dram_write_data_");
 321                 pw.println("    , dram_write_data_push_");
 322                 pw.println("    , dram_write_data_full");
 323                 pw.println("    , dram_read_data");
 324                 pw.println("    , dram_read_data_pop_");
 325                 pw.println("    , dram_read_data_empty");
 326                 pw.println("    , dram_read_data_latency");
 327             }
 328             if (filename.equals("ddr2")) {
 329                 pw.println("    , ddr2_addr_");
 330                 pw.println("    , ddr2_addr_r_");
 331                 pw.println("    , ddr2_addr_a");
 332                 pw.println("    , ddr2_isread_");
 333                 pw.println("    , ddr2_write_data_");
 334                 pw.println("    , ddr2_write_data_push_");
 335                 pw.println("    , ddr2_write_data_full");
 336                 pw.println("    , ddr2_read_data");
 337                 pw.println("    , ddr2_read_data_pop_");
 338                 pw.println("    , ddr2_read_data_empty");
 339                 pw.println("    , ddr2_read_data_latency");
 340             }
 341             if (filename.equals("video")) {
 342                 pw.println("    , vga_clk");
 343                 pw.println("    , vga_psave");
 344                 pw.println("    , vga_hsync");
 345                 pw.println("    , vga_vsync");
 346                 pw.println("    , vga_sync");
 347                 pw.println("    , vga_blank");
 348                 pw.println("    , vga_r");
 349                 pw.println("    , vga_g");
 350                 pw.println("    , vga_b");
 351                 pw.println("    , vga_clkout");
 352             }
 353             pw.println("        );");
 354             pw.println();
 355             pw.println("    input clk;");
 356             pw.println("    input rst;");
 357             if (filename.equals("debug")) {
 358                 pw.println("        output  ["+WIDTH_WORD+":0] out_d_;");
 359                 pw.println("        input   out_a;");
 360                 pw.println("        output  out_r_;");
 361             }
 362             if (filename.equals("dram")) {
 363                 pw.println("output  [31:0] dram_addr_;");
 364                 pw.println("output         dram_addr_r_;");
 365                 pw.println("input          dram_addr_a;");
 366                 pw.println("output         dram_isread_;");
 367                 pw.println("output  [63:0] dram_write_data_;");
 368                 pw.println("output         dram_write_data_push_;");
 369                 pw.println("input          dram_write_data_full;");
 370                 pw.println("input   [63:0] dram_read_data;");
 371                 pw.println("output         dram_read_data_pop_;");
 372                 pw.println("input          dram_read_data_empty;");
 373                 pw.println("input   [1:0]  dram_read_data_latency;");
 374             }
 375             if (filename.equals("ddr2")) {
 376                 pw.println("output  [31:0] ddr2_addr_;");
 377                 pw.println("output         ddr2_addr_r_;");
 378                 pw.println("input          ddr2_addr_a;");
 379                 pw.println("output         ddr2_isread_;");
 380                 pw.println("output  [63:0] ddr2_write_data_;");
 381                 pw.println("output         ddr2_write_data_push_;");
 382                 pw.println("input          ddr2_write_data_full;");
 383                 pw.println("input   [63:0] ddr2_read_data;");
 384                 pw.println("output         ddr2_read_data_pop_;");
 385                 pw.println("input          ddr2_read_data_empty;");
 386                 pw.println("input   [1:0]  ddr2_read_data_latency;");
 387             }
 388             if (filename.equals("video")) {
 389                 pw.println("input          vga_clk;");
 390                 pw.println("output         vga_psave;");
 391                 pw.println("output         vga_hsync;");
 392                 pw.println("output         vga_vsync;");
 393                 pw.println("output         vga_sync;");
 394                 pw.println("output         vga_blank;");
 395                 pw.println("output   [7:0] vga_r;");
 396                 pw.println("output   [7:0] vga_g;");
 397                 pw.println("output   [7:0] vga_b;");
 398                 pw.println("output         vga_clkout;");
 399             }
 400
 401             for(DockDescription bb : sd) {
 402                 String bb_name = bb.getName();
 403                 if (bb.isInputDock()) {
 404                     pw.println("        input   ["+WIDTH_WORD+":0] "+bb_name+"_d;");
 405                     pw.println("        input   "+bb_name+"_r_;");
 406                     pw.println("        wire    "+bb_name+"_r;");
 407                     pw.println("        assign  "+bb_name+"_r = "+bb_name+"_r_ & ~"+bb_name+"_d["+WIDTH_WORD+"];");
 408                     pw.println("        output  "+bb_name+"_a_;");
 409                     pw.println("        reg     "+bb_name+"_a;");
 410                     pw.println("        initial "+bb_name+"_a  = 0;");
 411                     pw.println("        reg     "+bb_name+"_f;");
 412                     pw.println("        initial "+bb_name+"_f  = 0;");
 413                     pw.println("        assign  "+bb_name+"_a_ = "+bb_name+"_a || "+bb_name+"_f;");
 414                 } else {
 415                     pw.println("        output  ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
 416                     pw.println("        input   "+bb_name+"_a;");
 417                     pw.println("        output  "+bb_name+"_r_;");
 418                     pw.println("        reg     "+bb_name+"_r;");
 419                     pw.println("        initial "+bb_name+"_r  = 0;");
 420                     pw.println("        assign  "+bb_name+"_r_ = "+bb_name+"_r;");
 421                 }
 422                 pw.println();
 423             }
 424
 425             pw.println(sd.getSection("fpga"));
 426
 427             pw.println("endmodule");
 428
 429             pw.flush();
 430             pw.close();
 431         } catch (Exception e) { throw new RuntimeException(e); }
 432     }
 433
 434 }