1 package edu.berkeley.fleet.fpga;
2 import edu.berkeley.fleet.api.*;
3 import edu.berkeley.fleet.two.*;
4 import edu.berkeley.fleet.*;
5 import java.lang.reflect.*;
6 import edu.berkeley.sbp.chr.*;
7 import edu.berkeley.sbp.misc.*;
8 import edu.berkeley.sbp.meta.*;
9 import edu.berkeley.sbp.util.*;
12 import static edu.berkeley.fleet.two.FleetTwoFleet.*;
13 import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
14 import edu.berkeley.fleet.api.*;
15 import edu.berkeley.fleet.api.Dock;
16 import edu.berkeley.fleet.two.*;
19 public class FpgaDock extends FleetTwoDock implements FabricElement {
21 private static final int INSTRUCTION_FIFO_SIZE = 12;
22 private static final int EPILOGUE_FIFO_SIZE = 0;
23 //private static final int DATA_FIFO_SIZE = 4;
24 private static final int DATA_FIFO_SIZE = 8;
26 private FpgaDestination dataDestination;
27 private FpgaDestination instructionDestination;
29 private Module.InstantiatedModule instance;
31 public Module.InstantiatedModule getInstance() { return instance; }
35 public Destination getDataDestination() { return dataDestination; }
36 public Destination getInstructionDestination() { return instructionDestination; }
37 public int getInstructionFifoSize() { return INSTRUCTION_FIFO_SIZE; }
39 FpgaDock(FpgaShip ship, DockDescription bbd) {
41 this.fpga = (Fpga)ship.getFleet();
42 this.instance = new Module.InstantiatedModule(((Fpga)ship.getFleet()).top, new DockModule(isInputDock()));
43 this.dataDestination = new FpgaDestination(this, this.instance.getInputPort("fabric_in"), false);
44 this.instructionDestination = new FpgaDestination(this, this.instance.getInputPort("instruction"), true);
45 Module.InstantiatedModule shipm = ship.getVerilogModule();
47 instance.getOutputPort("ship").connect(shipm.getInputPort(getName()));
49 shipm.getOutputPort(getName()).connect(instance.getInputPort("ship"));
54 // FabricElement methods //////////////////////////////////////////////////////////////////////////////
56 private FabricElement upstream;
57 public Module.SourcePort getOutputPort() { throw new RuntimeException(); }
58 public Module.Port getInputPort() { throw new RuntimeException(); }
59 public Path getPath(Destination dest,BitVector signal) { return getPath((FpgaDestination)dest, signal); }
60 public FpgaPath getPath(FpgaDestination dest,BitVector signal) { return upstream.getPath(dest, signal); }
61 public void addInput(FabricElement in, Module.Port inPort) { throw new RuntimeException(); }
62 public void addOutput(FabricElement out, Module.Port outPort) {
64 instance.getOutputPort("fabric_out").connect((Module.SinkPort)outPort);
67 public class TorpedoBranchModule extends Module {
68 public TorpedoBranchModule() {
69 super("torpedobranch");
70 Module.SourcePort in = createInputPort ("in", fpga.WIDTH_PACKET);
71 Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
72 Module.SinkPort torpedo = createOutputPort("torpedo", 0);
73 Module.StateWire busy = new StateWire("busy", false);
75 new Event(new Object[] { in, busy.isFull(), out },
76 new Action[] { in, busy.doDrain() });
77 new Event(new Object[] { in, busy.isEmpty(), out, torpedo, in.testMask(fpga.PACKET_IS_TOKEN) },
78 new Action[] { in, torpedo });
79 new Event(new Object[] { in, busy.isEmpty(), out, in.testMask(fpga.PACKET_IS_TOKEN).invert() },
80 new Action[] { busy.doFill(), out });
82 out.connectValue(in.getBits(fpga.PACKET_DATA));
86 public class RequeueModule extends Module {
87 public RequeueModule() {
89 Module.SourcePort fabric_in = createInputPort ("fabric_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
90 Module.SourcePort ondeck_in = createInputPort ("ondeck_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
91 Module.SourcePort abort = createInputPort ("abort", 1);
92 Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
94 Module.StateWire circulating = new StateWire("circulating", false);
95 Module.StateWire doResetFabric = new StateWire("doResetFabric", false);
96 Module.StateWire doResetOndeck = new StateWire("doResetOndeck", false);
98 out.connectValue(new MuxValue(circulating.isEmpty(), fabric_in, ondeck_in));
100 // always: discard one-shot instructions
101 new Event(new Object[] { doResetFabric.isFull(), out },
102 new Action[] { doResetFabric.doDrain(), fabric_in });
103 new Event(new Object[] { doResetOndeck.isFull(), out },
104 new Action[] { doResetOndeck.doDrain(), ondeck_in });
106 // Updating->Circulating transition
107 new Event(new Object[] { doResetFabric.isEmpty(),
108 doResetOndeck.isEmpty(),
109 circulating.isEmpty(),
111 fpga.TAIL.verilog(fabric_in.getName()),
113 fpga.HEAD.verilog(ondeck_in.getName()) },
114 new Action[] { circulating.doFill(),
118 // Circulating->Updating transition
119 new Event(new Object[] { doResetFabric.isEmpty(),
120 doResetOndeck.isEmpty(),
121 circulating.isFull(),
123 abort.getVerilog() },
124 new Action[] { circulating.doDrain(),
128 new Event(new Object[] { doResetFabric.isEmpty(),
129 doResetOndeck.isEmpty(),
130 circulating.isEmpty(),
132 "!"+fpga.TAIL.verilog(fabric_in.getName()) },
133 new Action[] { doResetFabric.doFill(),
135 new Event(new Object[] { doResetFabric.isEmpty(),
136 doResetOndeck.isEmpty(),
137 circulating.isEmpty(),
139 "!"+fpga.HEAD.verilog(ondeck_in.getName()) },
140 new Action[] { ondeck_in });
143 new Event(new Object[] { doResetFabric.isEmpty(),
144 doResetOndeck.isEmpty(),
145 circulating.isFull(),
147 "!"+abort.getVerilog() },
148 new Action[] { doResetOndeck.doFill(),
153 public class DockModule extends Module {
155 public DockModule(boolean inbox) {
156 super(inbox ? "inbox" : "outbox");
158 int dfifo_width = inbox ? fpga.getWordWidth()+1 : 1;
160 // FIXME: assumes fpga.DISPATCH_PATH is at top of word!!!
161 Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
162 Module dfifo_m = new FifoModule(DATA_FIFO_SIZE, dfifo_width);
164 Module.SourcePort instruction = createInputPort("instruction", fpga.WIDTH_PACKET);
165 Module.SourcePort fabric_in = createInputPort("fabric_in", fpga.WIDTH_PACKET);
167 // FIXME: at inboxes, no need for a full set of latches
168 Module.SinkPort fabric_out = createOutputPort("fabric_out", fpga.WIDTH_PACKET);
170 Module.InstantiatedModule dfifo = new Module.InstantiatedModule(this, dfifo_m);
172 fabric_in.connect(dfifo.getInputPort("in"));
173 dfifo.getInputPort("in").connectValue(
175 ? fabric_in.getBits(fpga.PACKET_SIGNAL)
176 : new CatValue(new Value[] {
177 fabric_in.getBits(fpga.PACKET_SIGNAL),
178 fabric_in.getBits(fpga.PACKET_DATA)
181 Module.SourcePort dfifo_out = dfifo.getOutputPort("out");
182 Module.SourcePort ship_out = !inbox ? createInputPort("ship", fpga.getWordWidth()+1) : null;
183 Module.SinkPort ship_in = inbox ? createOutputPort("ship", fpga.getWordWidth()+1) : null;
185 Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
186 Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
187 Module.Latch flag_a = new Latch("flag_a", 1);
188 Module.Latch flag_b = new Latch("flag_b", 1);
189 Module.Latch flag_c = new Latch("flag_c", 1);
190 Module.Latch flag_d = new Latch("flag_d", 1);
192 Module.SinkPort token_out = fabric_out;
193 Module.SourcePort token_in = dfifo_out;
194 Module.SinkPort data_out = inbox ? ship_in : fabric_out;
195 Module.SourcePort data_in = inbox ? dfifo_out : ship_out;
197 Module.InstantiatedModule ififo = new Module.InstantiatedModule(this, ififo_m);
198 Module.SinkPort ififo_in = ififo.getInputPort("in");
199 Module.SourcePort ififo_out = ififo.getOutputPort("out");
201 Module.InstantiatedModule torpedo_branch = new Module.InstantiatedModule(this, new TorpedoBranchModule());
202 instruction.connect(torpedo_branch.getInputPort("in"));
203 Module.SourcePort efifo_out = torpedo_branch.getOutputPort("out");
204 Module.SourcePort torpedo_branch_torpedo = torpedo_branch.getOutputPort("torpedo");
206 Module.InstantiatedModule fanout_module = new Module.InstantiatedModule(this, new FanoutModule(fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth));
207 Module.SinkPort fanout_module_in = fanout_module.getInputPort("in");
208 Module.SourcePort fanout_module_out0 = fanout_module.getOutputPort("out0");
209 Module.SourcePort fanout_module_out1 = fanout_module.getOutputPort("out1");
211 Module.InstantiatedModule requeue_module = new Module.InstantiatedModule(this, new RequeueModule());
212 Module.SinkPort requeue_fabric_in = requeue_module.getInputPort("fabric_in");
213 Module.SinkPort requeue_ondeck = requeue_module.getInputPort("ondeck_in");
214 Module.SinkPort requeue_abort = requeue_module.getInputPort("abort");
215 Module.SourcePort requeue_out = requeue_module.getOutputPort("out");
217 efifo_out.connect(requeue_fabric_in);
218 requeue_out.connect(ififo_in);
219 ififo_out.connect(fanout_module_in);
220 fanout_module_out0.connect(requeue_ondeck);
221 Module.SourcePort ondeck = fanout_module_out1;
223 WireValue decremented = new WireValue("decremented", Math.max(ilc.width,olc.width),
224 new SimpleValue("("+ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE).getVerilogTrigger()+
225 " ? {1'b0, olc} : ilc)-1"));
226 WireValue data_latch_output_p = new WireValue("data_latch_output",
227 inbox ? fpga.getWordWidth()+1 : fpga.getWordWidth(),
229 ? new SimpleValue(data_out.getName())
230 : new SimpleValue(data_out.getBits(fpga.PACKET_DATA).getVerilog()))
233 Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : data_out.getBits(fpga.PACKET_DATA).getVerilog());
234 Module.SourcePort data_latch_input = inbox ? data_in : data_in;
236 BitVector bv = new BitVector(fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1);
237 bv.set(fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth, true);
238 Value magic_standing_value = new ConstantValue(bv);
240 Trigger done_executing = new SimpleTrigger("((ilc==0) || (ilc==1) || !"+fpga.MOVE.verilog(ondeck.getName())+")");
242 String predicate_met =
245 "!"+fpga.MOVE.verilog(ondeck.getName())+" || (ilc!=0)"+
248 fpga.P_ALWAYS.verilog(ondeck.getName())+
250 fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==flag_d"+
253 " " + fpga.P_A.verilog(ondeck.getName())+" ? flag_a"+
254 ":" + fpga.P_B.verilog(ondeck.getName())+" ? flag_b"+
255 ":" + fpga.P_NOT_A.verilog(ondeck.getName())+" ? !flag_a"+
256 ":" + fpga.P_NOT_B.verilog(ondeck.getName())+" ? !flag_b "+
261 requeue_abort.connectValue(new SimpleValue("("+predicate_met+") && "+fpga.ABORT.verilog(ondeck.getName())));
264 new Event(new Object[] {
269 fpga.MOVE.verilog(ondeck.getName()),
270 "!"+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName()),
271 torpedo_branch_torpedo
275 torpedo_branch_torpedo,
276 new AssignAction(olc, new ConstantValue(new BitVector(olc.width).set(0))),
277 new AssignAction(flag_d, new ConstantValue(new BitVector(1).set(1))),
278 new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))
282 new Event(new Object[] { ondeck, "!("+predicate_met+")" },
283 new Action[] { ondeck,
284 new ConditionalAction(ondeck.testMask(fpga.MOVE),
285 new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1))))
288 new Event(new Object[] { ondeck,
292 "(!"+fpga.MOVE.verilog(ondeck.getName())+" || "+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName())+" || !"+torpedo_branch_torpedo.isFull()+")",
293 new ConditionalTrigger(ondeck.testMask(fpga.DI), data_in),
294 new ConditionalTrigger(ondeck.testMask(fpga.TI), token_in)
297 new ConditionalAction(new AndTrigger(done_executing, ondeck.testMask(fpga.MOVE)),
298 new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))),
299 new ConditionalAction(done_executing, ondeck),
300 new ConditionalAction(done_executing.invert(),
301 new AssignAction(ilc, new MuxValue(new TestValue(ilc, TestValue.TestType.EQ, magic_standing_value),
302 magic_standing_value,
304 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
305 new AssignAction(olc, new SimpleValue("data_latch_output"))),
306 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
307 new AssignAction(olc, ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE))),
308 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
309 new AssignAction(olc, new SimpleValue("olc==0 ? 0 : decremented"))),
311 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
312 new AssignAction(flag_d, new SimpleValue("data_latch_output==0"))),
313 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
314 new AssignAction(flag_d, new SimpleValue(ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE).getVerilog()+"==0"))),
315 new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
316 new AssignAction(flag_d, new SimpleValue("(olc==0 || olc==1)"))),
318 new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_DATA_LATCH),
319 new AssignAction(ilc, new SimpleValue("data_latch_output"))),
321 new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_IMMEDIATE),
322 new AssignAction(ilc, ondeck.getBits(fpga.SET_ILC_FROM_IMMEDIATE))),
323 new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_INFINITY),
324 new AssignAction(ilc, magic_standing_value)),
325 new ConditionalAction(ondeck.testMask(fpga.SHIFT),
326 new AssignAction(data_latch,
327 new SimpleValue("{ data_latch_output["+(fpga.getWordWidth()-1-fpga.SHIFT.valmaskwidth)+":0], "+
328 ondeck.getBits(fpga.SHIFT).getVerilog()+"}"))),
329 new ConditionalAction(ondeck.testMask(fpga.SET_IMMEDIATE),
330 new AssignAction(data_latch,
331 new SimpleValue("{ {"+(fpga.getWordWidth()-fpga.DataLatch_WIDTH)+
332 "{"+ondeck.getBits(fpga.SET_IMMEDIATE_EXTEND).getVerilog()+"}}, "+
333 ondeck.getBits(fpga.SET_IMMEDIATE).getVerilog()+" }"))),
334 new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
335 new AssignAction(flag_a, new_flag(ondeck.getBits(fpga.SET_FLAGS_A),flag_a,flag_b,flag_c))),
336 new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
337 new AssignAction(flag_b, new_flag(ondeck.getBits(fpga.SET_FLAGS_B),flag_a,flag_b,flag_c))),
338 new ConditionalAction(ondeck.testMask(fpga.MOVE),
339 new AssignAction(flag_c,
341 ? dfifo_out.getBits(dfifo_width-1, dfifo_width-1)
342 : new MuxValue(ondeck.testMask(fpga.DC),
343 ship_out.getBits(fpga.getWordWidth(), fpga.getWordWidth()),
344 dfifo_out.getBits(dfifo_width-1, dfifo_width-1))
346 new ConditionalAction(ondeck.testMask(fpga.DI), data_in),
347 new ConditionalAction(ondeck.testMask(fpga.DO), data_out),
348 new ConditionalAction(ondeck.testMask(fpga.FLUSH), data_out),
350 ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"),
351 new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
353 new ConditionalAction(ondeck.testMask(fpga.TI), token_in),
354 new ConditionalAction(ondeck.testMask(fpga.TO), token_out),
355 new ConditionalAction(ondeck.testMask(fpga.DC), new AssignAction(data_latch, data_latch_input)),
356 new AssignAction(token_out.getBits(fpga.PACKET_TOKEN),
357 new SimpleValue("("+fpga.TO.verilog(ondeck.getName())+")?1:0")),
358 new ConditionalAction(ondeck.testMask(fpga.PATH_DATA),
359 new AssignAction(new SimpleAssignable("{ "+token_out.getBits(fpga.PACKET_SIGNAL).getVerilog()+", "+
360 token_out.getBits(fpga.PACKET_DEST).getVerilog()+" }"),
361 data_latch_input.getBits(fpga.DISPATCH_PATH))),
362 new ConditionalAction(ondeck.testMask(fpga.PATH_IMMEDIATE),
363 new AssignAction(new SimpleAssignable("{ "+token_out.getBits(fpga.PACKET_SIGNAL).getVerilog()+", "+
364 token_out.getBits(fpga.PACKET_DEST).getVerilog()+" }"),
365 ondeck.getBits(fpga.PATH_IMMEDIATE)))
370 private Value new_flag(Value v, Value flag_a, Value flag_b, Value flag_c) {
371 Value[] vals = new Value[] {
372 new LogicValue(v.getBits(0,0), LogicValue.LogicType.AND, flag_c.invertBits()),
373 new LogicValue(v.getBits(1,1), LogicValue.LogicType.AND, flag_c),
374 new LogicValue(v.getBits(2,2), LogicValue.LogicType.AND, flag_b.invertBits()),
375 new LogicValue(v.getBits(3,3), LogicValue.LogicType.AND, flag_b),
376 new LogicValue(v.getBits(4,4), LogicValue.LogicType.AND, flag_a.invertBits()),
377 new LogicValue(v.getBits(5,5), LogicValue.LogicType.AND, flag_a),
379 Value ret = new ConstantValue(new BitVector(1).set(0));
380 for(int i=0; i<vals.length; i++)
381 ret = new LogicValue(ret, LogicValue.LogicType.OR, vals[i]);