1 module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
4 input [(`BRAM_ADDR_WIDTH-1):0] a;
5 input [(`BRAM_ADDR_WIDTH-1):0] dpra;
6 input [(`BRAM_DATA_WIDTH-1):0] di;
7 output [(`BRAM_DATA_WIDTH-1):0] spo;
8 output [(`BRAM_DATA_WIDTH-1):0] dpo;
9 reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
10 reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
11 reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
12 always @(posedge clk) begin
18 assign spo = ram[read_a];
19 assign dpo = ram[read_dpra];