src/edu/berkeley/fleet/fpga/bram.inc

   1 /* bram.inc */
   2 module `BRAM_NAME(clk, rst, we, a, dpra, di, spo, dpo);
   3     input  clk;
   4     input  rst;
   5     input  we;
   6     input  [(`BRAM_ADDR_WIDTH-1):0] a;
   7     input  [(`BRAM_ADDR_WIDTH-1):0] dpra;
   8     input  [(`BRAM_DATA_WIDTH-1):0] di;
   9     output [(`BRAM_DATA_WIDTH-1):0] spo;
  10     output [(`BRAM_DATA_WIDTH-1):0] dpo;
  11     reg    [(`BRAM_DATA_WIDTH-1):0] ram [((`BRAM_SIZE)-1):0];
  12     reg    [(`BRAM_ADDR_WIDTH-1):0] read_a;
  13     reg    [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
  14     always @(posedge clk) begin
  15         if (we)
  16             ram[a] <= di;
  17         read_a <= a;
  18         read_dpra <= dpra;
  19     end
  20     assign spo = ram[read_a];
  21     assign dpo = ram[read_dpra];
  22 endmodule
  23 /* bram.inc */