1 `input(write_addr_r, write_addr_a, write_addr_a_, [(`DATAWIDTH-1):0], write_addr_d)
2 `input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
3 `output(write_done_r, write_done_r_, write_done_a, [(`DATAWIDTH-1):0], write_done_d_)
4 `defreg(write_done_d_, [(`DATAWIDTH-1):0], write_done_d)
8 assign bram_we_ = bram_we;
9 wire [(`BRAM_DATA_WIDTH-1):0] bram_read_data;
10 reg [(`BRAM_ADDR_WIDTH-1):0] bram_write_address;
11 wire [(`BRAM_ADDR_WIDTH-1):0] bram_read_address;
12 reg [(`BRAM_DATA_WIDTH-1):0] bram_write_data;
13 wire [(`BRAM_DATA_WIDTH-1):0] bram_write_data_;
14 assign bram_write_data_ = bram_write_data;
15 `BRAM_NAME mybram(clk,
16 bram_we_, bram_write_address,
17 bram_read_address, bram_write_data_,
18 not_connected, bram_read_data);